Abstract: A peripheral component interconnect express (PCIE) data transmission system and link state managing method thereof are disclosed. The PCIE data transmission system includes an upstream device, a downstream device and a link. When the link is in a first link state, the downstream device and the upstream device transmit data normally via the link. When the upstream device outputs a turn-off signal to the downstream device, a time period is counted. The downstream device outputs an acknowledging signal to response the turn-off signal. If the upstream device does not receive the acknowledging signal within the time period, the link is transited from the first link state to second link state to remove the power of the link.

Abstract: In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device is ready to change from a first state to a second state in a specified duration. A negotiating procedure is performed to have the first link and the second link enter the second state simultaneously if the second link is detected to be in the first state within the specified duration.

Abstract: A serial transceiver transmits at least one package of a data link layer and includes at least one channel including at least one transmitting module and at least one receiving module, a generating module and a controlling module. The channel is for transmitting the corresponding package. The transmitting module transmits the corresponding package and generates a transmitting time signal. The receiving module receives the package transmitted from the corresponding transmitting module and generates a receiving time signal. The generating module generates a target delay time signal. The controlling module receives the target delay time signal, transmitting time signals and receiving time signals, and generates a delay time signal for the corresponding receiving module according to the target delay time signal, the transmitting time signal and the receiving time signal.

Abstract: A method for link bandwidth management between two devices in communication through a bandwidth-adjustable bus in a computer system determines which of a speed negotiation priority and a width negotiation priority is higher when the change condition is activated. An original width of the bus is changed to a target width first while remaining an original speed of the bus unchanged when the width negotiation priority is higher, and then optionally changing the original speed to a target speed. On the other hand, an original speed of the bus is changed to the target speed first while remaining the original width of the bus unchanged when the speed negotiation priority is higher, and then optionally changing the original width to the target width. The bus operates at a target bandwidth with the target width and the target speed without disabling the link state or powering down the computer system.

Abstract: A method for link bandwidth management between two devices in communication through a bus in a computer system. Whether a change condition of the bus having a link is activated is monitored. Change a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated. The bus will operate at the target bandwidth without disabling the link or powering down the computer system if subsequent failure speed management and unreliable speed management have passed.

Abstract: In a data synchronization method for use in a multilane data buffer device including at least a first data buffer in a first lane and a second data buffer in a second lane, when there is a first invalid data transmitted in the first lane to be written into the first data buffer prior to a second invalid data transmitted in the second lane to be written into the second data buffer, a first synchronizing invalid data is written and inserted into the second data buffer. The first invalid data and the first synchronizing invalid data are written into the first data buffer and the second data buffer at synchronous positions. After the first synchronizing invalid data is written into the second data buffer, the second invalid data is discarded from entering the second data buffer.

Abstract: The disclosure relates to a link bandwidth management which is initiated either by software or hardware, and related negotiation failure or unreliable management, and also related hardware autonomous negotiation priority. By introducing flexible bandwidth management, this invention can resolve the problems of prior art. Different link bandwidth can be set for different applications, which can help to achieve both good performance and power savings.

Abstract: In a state negotiation method of a PCI-E upstream device supporting multiple downstream configurations, a state of a second link asserted by a second state machine of the PCI-E upstream device is detected when a first link asserted by a first state machine of the PCI-E upstream device is ready to change from a first state to a second state in a specified duration. A negotiating procedure is performed to have the first link and the second link enter the second state simultaneously if the second link is detected to be in the first state within the specified duration.

Abstract: A PCI Express system and a method of transitioning link state thereof are provided. The PCI Express system has an upstream device, a downstream device and a link. The upstream device and the downstream device transmit data packets to both via the link, but when the link is in a first link state, data packet transmission is forbidden. In the beginning, the link is in a second link state and data packet transmission is normal. The upstream device transmits a data packet via the link to the downstream device. A time period is counted when receiving the data packet. The downstream device asserts an acknowledge packet to the upstream device to response the data pocket. After the timer is expired, the link is transited to the first link state.

Abstract: A peripheral component interconnect express (PCIE) data transmission system and link state managing method thereof are disclosed. The PCIE data transmission system includes an upstream device, a downstream device and a link. When the link is in a first link state, the downstream device and the upstream device transmit data normally via the link. When the upstream device outputs a turn-off signal to the downstream device, a time period is counted. The downstream device outputs an acknowledging signal to response the turn-off signal. If the upstream device does not receive the acknowledging signal within the time period, the link is transited from the first link state to second link state to remove the power of the link.