Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: A communication system includes a time-to-digital converter, a digital low-pass filter, and a digital signal processor. The time-to-digital converter receives an in-phase signal of a frequency-shift keying signal and to generate a digital signal according to the in-phase signal. The digital low-pass filter receives the digital signal and to generate a filtered signal including N continuous words according to the digital signal. The digital signal processor divides up the N continuous words into N/2 word sets in order, wherein each of the N/2 word sets includes a first word and a second word, and if a difference between the first word and the second word meets a predetermined condition, the digital signal processor generates an output data and an output clock according to all the first words and the second words that have difference which meets the predetermined condition.

Abstract: A communication system includes a time-to-digital converter, a digital low-pass filter, and a digital signal processor. The time-to-digital converter receives an in-phase signal of a frequency-shift keying signal and to generate a digital signal according to the in-phase signal. The digital low-pass filter receives the digital signal and to generate a filtered signal including N continuous words according to the digital signal. The digital signal processor divides up the N continuous words into N/2 word sets in order, wherein each of the N/2 word sets includes a first word and a second word, and if a difference between the first word and the second word meets a predetermined condition, the digital signal processor generates an output data and an output clock according to all the first words and the second words that have difference which meets the predetermined condition.

Abstract: A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

Abstract: A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Abstract: A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Abstract: A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits.

Abstract: A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).

Abstract: A voltage detector circuit of a nonvolatile memory integrated circuit for determining the voltage potential of a supply voltage is provided. The voltage detector includes a first MOS device, a second MOS device, a bias circuit for adjusting the current through the first and second MOS devices that is responsive to the level of the supply voltage, and an output circuit that provides an output signal indicating the level of the supply voltage. The bias circuit may comprise a voltage divider circuit which provides a predetermined ratio of the supply voltage to the gate of one or both of the MOS devices. The voltage divider circuit may comprise MOS devices configured as resistive devices in series. The current through the MOS devices is provided to the output circuit, and the output circuit utilizes a measure of the difference in the current levels to determine the level of the voltage supply and provide the appropriate output signal.

Abstract: In a floating gate memory that has a buffer that can be coupled to a set of floating gate memory cells in the memory, a method of writing to a selected portion of the set of floating gate cells. For example, a method of writing a byte to a floating gate memory where the memory uses a page buffer reads and writes to an entire row of cells at a time. Store contents of the set of floating gate cells into the buffer, store the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells, and store contents of the buffer into the set of floating gate cells. An improved floating gate memory is disclosed in which data may be loaded into a portion of the floating gate cells in a set of cells that may be coupled to a buffer.

Abstract: A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.

Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pump are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Abstract: A method for having a modem detect a call waiting signal from a telephone network is described. A first signal detector generates a first signal when detecting a carrier signal from the telephone network, and generates a second signal when not detecting the carrier signal. If the first signal detector generates the second signal for a first predetermined time interval and if the first signal detector generates the first signal for a second predetermined time interval subsequent to the first predetermined time interval a second signal detector is connected to the telephone network to detect if energy is present from the telephone network for a third predetermined time interval subsequent to the second predetermined time interval.