Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract: A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract: At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.

Abstract: A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off.

Abstract: A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. The first pull-up transistor is connected between an external power supply terminal and an output terminal and responds to a first control signal which swings between an internal power supply voltage and a ground voltage. The external power supply terminal receives an external power supply having a voltage level higher than the voltage level of the internal power supply. The first pull-up transistor provides an output signal to the output terminal having the voltage level of the internal power supply voltage minus a predetermined voltage drop. The second pull-up transistor is connected between the internal power supply voltage terminal and the output terminal.

Abstract: A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled.

Abstract: The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line.

Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Abstract: A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

Abstract: An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with each bank including at least two rows of memory cells. Each of the data lines extends along one of the columns of memory cells so that each of the data lines extends along memory cells from each of the banks of memory cells. The memory cell selector includes a row decoder which selects one of the plurality of rows, a column decoder which selects one of the plurality of columns, and a bank decoder which selects one of the banks. The connector connects one of the memory cells to a respective data line in response to the memory cell selector. Accordingly, data from only one of the memory cells is provided on a respective one of the data lines at any point and time.