Abstract: Embodiments of the disclosure provide an image processing method and an image processing device. The method includes the following. A first image is obtained, and the first image is down-sampled into a second image. A first resolution parameter combination of each second pixel in the second image is obtained. A target pixel among the first pixels is selected, and second pixels corresponding to the target pixel among the second pixels are accordingly obtained. A comparison result is determined between the target pixel and each second pixel corresponding to the target pixel, and a candidate pixel among the second pixels corresponding to the target pixel is accordingly selected. A second resolution parameter combination of the target pixel is selected based on the first resolution parameter combination of the candidate pixel. The target pixel is converted into an output pixel based on the second resolution parameter combination.

Abstract: An image processing method and an image processing apparatus are provided. In the method, first encoding is performed on an input image, to output a first noisy image. De-noising is performed on the first noisy image, to output a first de-noised image. De-noising is performed on the input image according to the first de-noised image, to output a first image.

Abstract: A computing circuit and a data processing method based on a convolutional neural network and a computer readable storage medium are provided. Input data is obtained from a memory. A first computation is performed on first part data of the input data to obtain first output data. The first output data is buffered in a first buffer. When the buffered first output data is greater than a first predetermined data amount, a second computation is performed on the first output data to obtain second output data. The second output data is buffered in a second buffer. Third output data obtained by performing a third computation on the second output data is output to the memory. When performing the second computation on the first output data, the first computation is continuously performed on the input data. Accordingly, the number of accesses of the memory can be reduced.

Abstract: The application provides an AI algorithm operation accelerator and method, a computing system, and a non-transitory computer readable media. The AI algorithm operation accelerating method includes steps of: A. reading an input data and a descriptor from a memory unit, wherein the descriptor includes a weight data; B. performing a first part of the input data and a first part of the weight data by a first operator for generating a first operation result; C. registering the first operation result; D. when the first operation result reaches a predetermined data amount, triggering a second operator to perform the first operation result and a second part of the weight data by the second operator for generating a second operation result; and E. writing the second operation result into the memory unit.

Abstract: An accelerated access apparatus and reading and writing methods thereof are described. A processing unit is used to determine whether the continuation state of a plurality of first address parameters of first request signals. Each first request signal has a first address length. When the first address parameters are continuous thereamong, the processing unit converts one of the second request signals into a second reading command which has a second reading address and a second reading address length. The second reading address length is greater than one of the first address lengths. The processing unit executes the second reading command to read data content to be stored in a buffer unit based on the second reading address and the second reading address length for responding to the second request signals.

Abstract: An accelerated access apparatus and reading and writing methods thereof are described. A processing unit is used to determine whether the continuation state of a plurality of first address parameters of first request signals. Each first request signal has a first address length. When the first address parameters are continuous thereamong, the processing unit converts one of the second request signals into a second reading command which has a second reading address and a second reading address length. The second reading address length is greater than one of the first address lengths. The processing unit executes the second reading command to read data content to be stored in a buffer unit based on the second reading address and the second reading address length for responding to the second request signals.

Abstract: A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.

Abstract: A communication system compatible to universal serial bus (USB) and method thereof are described. The communication system includes a client electronic device and a remote electronic device. The client electronic device establishes a communication link to the peripheral device connected to the remote electronic device. The client electronic device has a virtual host controller unit and a client application program module. The virtual host controller unit receives the control command and stores the control command. The client application program module sends the control command. The remote electronic device has a remote application program module and a physical host controller unit. The remote application program module analyzes the control command from the client application program module. The physical host controller unit performs the analyzed control command.

Abstract: An automatic feedback adjustment device for a digital antenna includes a digital antenna unit, a trafficator, a tuner, a demodulator, an antenna direction driver unit, a secondary controller, and a primary controller. The digital antenna unit is a digital video/broadcasting antenna system. The trafficator is connected to the digital antenna unit to retrieve direction data associated with the actual elevation angle and direction. The tuner is connected to the digital antenna unit and the demodulator is connected to the tuner in order to receive and convert a transmission signal from a transmission terminal into the video data and a received-signal quality signal. The antenna direction driver unit is connected to the digital antenna unit in order to drive adjustment of direction and elevation angle of the antenna.

Abstract: A storage system for improving efficiency in accessing flash memory and method for the same are disclosed. The present invention provides a cache unit for temporarily storing data prior to writing in the flash memory or reading from the flash memory. In reading process, after data stored in a flash memory is accessed by a host, the cache unit holds the data. Upon subsequent read requests to read the same data, the data is cached accordingly, thereby shortening a preparation time for reading the data from the flash memory. In writing process, a host requests write a series of requests to write data into the flash memory, the data is gathered and is stored in the cache unit until the cache unit is full. A cluster of data in the cache unit is accordingly written into the flash memory, so that a preparation time for writing the data into the flash memory is also shortened.

Abstract: A method for filtering the SDTV channels in a DVB is provided, including the following steps: using the video frequency ID and center frequency of the SDTV channel of the user's choice to look up a table to obtain at least a remaining video frequency ID different from the video frequency ID of the SDTV channel, while the remaining video frequency ID having the same center frequency as the SDTV channel; configuring a plurality of registers in the controller; and the controller discarding a plurality of DVB packets according to the registers. The controller can be either a PCI_EXPRESS controller or a USB controller.

Abstract: The proposed invention discloses a card reader controlling apparatus based on Secure Digital (SD) protocol, which comprises a high-speed bus interface, at least one SD host, at least one SD connection interface and SDIO connection interface (SD/SDIO interface), at least one bridge, and at least one other specific memory card connecting interface. The card reader controlling apparatus according to the proposed invention is capable of directly accessing data from/to an input/output device compatible with the SDIO connection interface (e.g. an SD card) or one other specific memory card via the high-speed bus interface. Thus, multiple format conversions performed by other peripheral bus interfaces (such as an USB interface) as the prior art can be by-passed or eliminated.

Abstract: An automatic feedback adjustment device for a digital antenna includes a digital antenna unit, a trafficator, a tuner, a demodulator, an antenna direction driver unit, a secondary controller, and a primary controller. The digital antenna unit is a digital video/broadcasting antenna system. The trafficator is connected to the digital antenna unit to retrieve direction data associated with the actual elevation angle and direction. The tuner is connected to the digital antenna unit and the demodulator is connected to the tuner in order to receive and convert a transmission signal from a transmission terminal into the video data and a received-signal quality signal. The antenna direction driver unit is connected to the digital antenna unit in order to drive adjustment of direction and elevation angle of the antenna.

Abstract: A method for filtering the SDTV channels in a DVB is provided, including the following steps: using the video frequency ID and center frequency of the SDTV channel of the user's choice to look up a table to obtain at least a remaining video frequency ID different from the video frequency ID of the SDTV channel, while the remaining video frequency ID having the same center frequency as the SDTV channel; configuring a plurality of registers in the controller; and the controller discarding a plurality of DVB packets according to the registers. The controller can be either a PCI_EXPRESS controller or a USB controller.

Abstract: A system, related apparatus, method and a computer accessible storage medium for operation environment migration are provided. The system includes a first PC, a second PC, and a USB migration cable having a first USB connector and a second USB connector. The USB migration cable includes a first USB connector, a second USB connector, a first USB controller coupled to the first USB connector, having an embedded first flash memory storing a non-volatile first firmware for operating the first USB controller, and a second USB controller coupled to the first USB controller, having an embedded second flash memory storing a non-volatile second firmware for operating the second USB controller, where the USB migration device uses the first USB controller to couple a first PC and the second USB controller to couple a second PC so that the second PC can automatically execute the drivers and the applications installed in the first PC to operate the USB migration device according to the autorun image file.

Abstract: A memory card reading/writing device includes a receptacle for directly receiving and accessing a first memory card and an adaptor defining a receiving space for receiving a second memory card that is different from the first memory card. The adaptor is receivable in the receptacle for electrically connecting the second memory card to the receptacle. A control circuit that is in electrical connection with the receptacle is connectable to a USB interface of for example a computer system for transfer of data between the memory cards and the computer systems. The control circuit includes first and second accessing devices for respectively and selectively accessing the first and second memory cards and a device for conversion of USB interfaced data transfer whereby data is transferred between the memory card and the USB host.