Abstract: A system for generating compensation pixel data for pixel data having adjacent values. The compensation pixel data is the pixel data adjusted by a value in order to perform an effect with the pixel data. The system has a comparator for determining whether the pixel data varies between adjacent values. Furthermore, the system includes a look-up table in communication with the comparator. The look-up table replaces the subsequent value of the pixel data with the compensation pixel data only when the preceding value of the pixel data is different than the subsequent value thereby reducing the number of look-ups for the compensation pixel data.

Abstract: In the present invention, an apparatus and method for performing alpha blending calculations in a fast and efficient manner is disclosed. When implemented as an integrated circuit, the apparatus of the present invention occupies reduced area. The apparatus comprises a plurality of multiplexers and an adder. Each of multiplexers is configured to receive a bit value, ?i, of the digital value alpha, ?. Each of the plurality of multiplexers is configured to receive the first and second digital image values. Each of the plurality of multiplexers is also configured to direct to outputs of the multiplexers either the first or second digital image value responsive to the bit value, ?i. Each of the outputs of the plurality of multiplexers is shifted left according to the order of the bit values, ?i, to produce a plurality of left-shifted outputs. The adder is produces the sum of the left-shifted outputs.

Abstract: In the present invention, an apparatus and method for performing alpha blending calculations in a fast and efficient manner is disclosed. When implemented as an integrated circuit, the apparatus of the present invention occupies reduced area. The apparatus comprises a plurality of multiplexers and an adder. Each of multiplexers is configured to receive a bit value, ?1, of the digital value alpha, ?. Each of the plurality of multiplexers is configured to receive the first and second digital image values. Each of the plurality of multiplexers is also configured to direct to outputs of the multiplexers either the first or second digital image value responsive to the bit value, ?i. Each of the outputs of the plurality of multiplexers is shifted left according to the order of the bit values, ?1, to produce a plurality of left-shifted outputs. The adder is produces the sum of the left-shifted outputs.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.