Abstract: A system includes an interconnect within an integrated circuit, and a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the interconnect. The system also includes a memory controller that is coupled to the interconnect. The memory controller is capable of selecting the internal SRAM and allocating the internal SRAM for storage accessible by one or more devices external to the first fuse-disabled integrated peripheral.

Abstract: An apparatus and system provide an optimizing content processing throughput for systems on chips (“SoCs”). A Packet Processing Memory Controller Cache (“PPMCC”) on an SoC according to an embodiment of the present invention may enable the SoC to store content packets within the SoC, thus eliminating the need to write to and read from external memory. Additionally, by utilizing Quality of Service (“QoS”) tags for the content packets received by the SoC, PPMCC may enforce a unique caching policy which optimizing content processing. Finally, an Address Translation Lookup Table (“ATLT”) on the SoC enables packet processing controllers on the SoC to route packets directly amongst themselves by identifying the source and destination of each content packet.

Abstract: A system, device, and method are disclosed. In one embodiment the system includes an interconnect within an integrated circuit. The system also includes a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the interconnect. The system also includes a memory controller that is coupled to the interconnect. The memory controller is capable of selecting the internal SRAM and allocating the internal SRAM for storage accessible by one or more devices external to the first fuse-disabled integrated peripheral.

Abstract: An apparatus and system provide an optimizing content processing throughput for systems on chips (“SoCs”). A Packet Processing Memory Controller Cache (“PPMCC”) on an SoC according to an embodiment of the present invention may enable the SoC to store content packets within the SoC, thus eliminating the need to write to and read from external memory. Additionally, by utilizing Quality of Service (“QoS”) tags for the content packets received by the SoC, PPMCC may enforce a unique caching policy which optimizing content processing. Finally, an Address Translation Lookup Table (“ATLT”) on the SoC enables packet processing controllers on the SoC to route packets directly amongst themselves by identifying the source and destination of each content packet.

Abstract: An apparatus that includes a multi-ported memory controller unit to control access to a memory external to the memory controller and comprising port interfaces coupled to the masters. Each master is capable of generating a transaction request with the memory.