Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a BEOL layer, a plurality of first metal structures and a plurality of second metal structures. The substrate has a first side and a second side opposite to the first side. The BEOL layer is disposed on the first side of the substrate. The first metal structures penetrate the substrate. The second metal structures are disposed in the substrate, extending from the second side towards the first side of the substrate, corresponding to the first metal structures.

Abstract: A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

Abstract: A method for forming a die package structure, including disposing a plurality of dies on a carrier substrate, wherein the top surface of each die has a plurality of signal junctions. The method also includes forming a vertical wire on each of the signal junctions, forming a supporting dielectric layer on the carrier substrate, wherein the supporting dielectric layer covers the dies and exposes the top of the vertical wires, and forming a plurality of redistribution traces on the supporting dielectric layer, wherein the redistribution traces are electrically connected to each of the vertical wires. The method further includes forming a bump at the bonding site of each of the redistribution traces, and performing a cutting process to singulate the dies.

Abstract: A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

Abstract: A package structure and its manufacturing method are provided. The package structure includes a substrate with a recess, and a first MEMS chip, a first intermediate chip, a second MEMS chip and a first capping plate sequentially formed on the substrate. The lower surface of the first MEMS chip has a first sensor or a microactuator. The upper surface of the second MEMS chip has a second sensor or a microactuator. The first intermediate chip has a through-substrate via, and includes a signal conversion unit, a logic operation unit, a control unit, or a combination thereof. The package structure includes at least one of the first sensor and the second sensor.

Abstract: Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Abstract: Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Abstract: A package structure and its manufacturing method are provided. The package structure includes a substrate with a recess, and a first MEMS chip, a first intermediate chip, a second MEMS chip and a first capping plate sequentially formed on the substrate. The lower surface of the first MEMS chip has a first sensor or a microactuator. The upper surface of the second MEMS chip has a second sensor or a microactuator. The first intermediate chip has a through-substrate via, and includes a signal conversion unit, a logic operation unit, a control unit, or a combination thereof. The package structure includes at least one of the first sensor and the second sensor.

Abstract: Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Abstract: Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Abstract: A conductive pillar bump includes a first conductive portion and a second conductive portion. The second conductive portion is located on the first conductive portion. A sidewall of the second conductive portion has at least one trench. The trench extends from a top portion of the second conductive portion to a bottom portion of the second conductive portion. The trench exposes a portion of a top surface of the first conductive portion.

Abstract: Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Abstract: Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.

Abstract: A wire bonding structure and a method of manufacturing the same are provided. The wire bonding structure includes a bonding pad structure, a protection layer and a bonding wire. The bonding pad structure includes a bonding pad and a conductive layer. The bonding pad has an opening. The conductive layer is electrically connected to the bonding pad. At least a portion of the conductive layer is located in the opening of the bonding pad and laterally surrounded by the bonding pad. The protection layer at least covers a portion of a surface of the bonding pad structure. The bonding wire is bonded to the conductive layer of the bonding pad structure.

Abstract: Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

Abstract: Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Abstract: A session-based remote management system and a load balance controlling method are provided. The session-based remote management system includes a plurality of client servers, a load balancing server, a plurality of local databases, a shared database and a monitor server. The session-based remote management system is adapted for a plurality of clients coupling to a plurality of local databases and a shared database through a plurality of client servers. The load balance controlling method includes following steps. A computing performance of the clients and the client servers are analyzed. The clients are dispatched to the client servers based on the computing performance of the clients and the client servers. A crash probability of the client servers are dynamically predicted to obtain a health value.