Patents by Inventor Jin-Ning Sung
Jin-Ning Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10096482Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.Type: GrantFiled: August 10, 2015Date of Patent: October 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Keung Hui, Jin-Ning Sung, Jong-I Mou, Soon-Kang Huang, Yen-Di Tsen
-
Patent number: 9477219Abstract: A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.Type: GrantFiled: March 25, 2010Date of Patent: October 25, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Hsu, Jin-Ning Sung, Shin-Rung Lu, Jong-I Mou
-
Publication number: 20150348797Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Keung Hui, Jin-Ning Sung, Jong-I Mou, Soon-Kang Huang, Yen-Di Tsen
-
Patent number: 9102033Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.Type: GrantFiled: November 24, 2010Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keung Hui, Jin-Ning Sung, Huang Soon Kang, Yen-Di Tsen, Jong-I Mou
-
Patent number: 8549012Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.Type: GrantFiled: May 12, 2010Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Jin-Ning Sung, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
-
Patent number: 8437870Abstract: System and method for implementing a VM APC platform are described. In one embodiment, the VM APC system comprises a process tool for processing a plurality of wafers, a metrology tool for measuring a sample wafer of the plurality of wafers and generating actual metrology data therefor, and a VM model for predicting metrology data for each of the plurality of wafers. The actual metrology data is received from the metrology tool and used to update the VM model. Key variables of the virtual metrology model are updated only in response to a determination that the VM model is inaccurate and parameters of the VM model are updated responsive to receipt of the actual metrology data for the sample wafer of the plurality of wafers. The system also includes an APC controller for receiving the predicted metrology data and the actual metrology data and controlling an operation of the process tool based on the received data.Type: GrantFiled: June 5, 2009Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Andy Tsen, Jin-Ning Sung
-
Patent number: 8394719Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.Type: GrantFiled: May 12, 2011Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-I Mou, Yen-Wei Cheng
-
Publication number: 20120129431Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.Type: ApplicationFiled: November 24, 2010Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: KEUNG HUI, Jin-Ning Sung, Huang Soon Kang, Yen-Di Tsen, Jong-I Mou
-
Publication number: 20110282885Abstract: In accordance with an embodiment, a method for exception handling comprises accessing an exception type for an exception, filtering historical data based on at least one defined criterion to provide a data train comprising data sets, assigning a weight to each data set, and providing a current control parameter. The data sets each comprise a historical condition and a historical control parameter, and the weight assigned to each data set is based on each historical condition. The current control parameter is provided using the weight and the historical control parameter for each data set.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Jin-Ning Sung, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
-
Publication number: 20110238197Abstract: A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Hsu, Jin-Ning Sung, Shin-Rung Lu, Jong-I Mou
-
Publication number: 20110213478Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method comprising obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer; modeling a process variable of the process as a function of the low resolution metrology data to generate a low-resolution process model; and modeling the process variable as a function of the high resolution metrology data to generate a high-resolution process model.Type: ApplicationFiled: May 12, 2011Publication date: September 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-l Mou, Yen-Wei Cheng
-
Patent number: 7951615Abstract: One embodiment is a method for fabricating ICs from a semiconductor wafer. The method includes performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further includes removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.Type: GrantFiled: April 1, 2009Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-I Mou
-
Publication number: 20100312374Abstract: System and method for implementing a VM APC platform are described. In one embodiment, the VM APC system comprises a process tool for processing a plurality of wafers, a metrology tool for measuring a sample wafer of the plurality of wafers and generating actual metrology data therefor, and a VM model for predicting metrology data for each of the plurality of wafers. The actual metrology data is received from the metrology tool and used to update the VM model. Key variables of the virtual metrology model are updated only in response to a determination that the VM model is inaccurate and parameters of the VM model are updated responsive to receipt of the actual metrology data for the sample wafer of the plurality of wafers.Type: ApplicationFiled: June 5, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Feng Tsai, Andy Tsen, Jin-Ning Sung
-
Publication number: 20100255613Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method for fabricating ICs from a semiconductor wafer comprising performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first measurement to generate metrology calibration data, wherein the metrology calibration data includes an effective portion and a non-effective portion. The method further comprises removing the non-effective portion from the metrology calibration data and modeling the effective portion with a metrology calibration model; combining the metrology calibration model with a first process model to generate a multi-resolution model, wherein the first process model models an input-output relationship of the first process; and analyzing a response of the multi-resolution model and second measurement data to control performance a second process.Type: ApplicationFiled: April 1, 2009Publication date: October 7, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Andy Tsen, Jin-Ning Sung, Po-Feng Tsai, Jong-I Mou