Abstract: An analog-to-digital converter (ADC) circuit includes an ADC module configured to convert an analog input signal into an original digital output signal, an error detection module configured to detect overflow of the original digital output signal due to the analog input signal being out of an input dynamic range of the ADC module and determine a current state of the original digital output signal as a normal state or an error state, and a correction module configured to, in response to the current state of the original digital output signal being the normal state, output a corrected digital output signal based on the original digital output signal and, in response to the current state of the original digital output signal being the error state, output the corrected digital output signal based on a replacement output signal for replacing the original digital output signal.

Abstract: A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.

Abstract: A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory elements configured to store a plurality of weights and to be controlled according to a plurality of input signals respectively and a bit line coupled to the plurality of nonvolatile memory elements; and a computation output circuit configured to generate a computation signal corresponding to an inner product between an input vector corresponding to the plurality of input signals and a weight vector corresponding to the plurality of weights.

Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

Abstract: A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.

Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

Abstract: A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory elements configured to store a plurality of weights and to be controlled according to a plurality of input signals respectively and a bit line coupled to the plurality of nonvolatile memory elements; and a computation output circuit configured to generate a computation signal corresponding to an inner product between an input vector corresponding to the plurality of input signals and a weight vector corresponding to the plurality of weights.