Patents by Inventor Jin RAO

Jin RAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421108
    Abstract: A method includes: forming, on a substrate (10), an epitaxial layer (11) and a source conducting layer (21), where the epitaxial layer includes a first via, to form a first epitaxial layer (101) of the first transistor and a second epitaxial layer (102) of the second transistor; the source conducting layer includes a first source (211) of the first transistor and a second source (212) of the second transistor; and an edge of the first source (211) is flush with an edge of the first epitaxial layer (101) close to a side of the first via, and an edge of the second source (212) is flush with an edge of the second epitaxial layer (102) close to a side of the first via; forming a first conducting layer (13) in the first via; forming a second via; and forming a second conducting layer (14) in the second via.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shuiming Li, Haijun Li, Zhili Zhang, Tao Liu, Jin Rao
  • Publication number: 20240274688
    Abstract: The present disclosure relates to semiconductor devices, manufacturing methods, a power amplification circuits, and electronic devices. One example semiconductor device includes a substrate, a channel layer and a barrier layer sequentially disposed on the substrate in a stacked manner, a source, a gate, and a drain disposed on the barrier layer, a backside via through a region from the substrate to the barrier layer below the source, and a backside conductive layer covering the backside via and a back surface of the substrate, where the source is in contact with and connected to the backside conductive layer.
    Type: Application
    Filed: March 13, 2024
    Publication date: August 15, 2024
    Inventors: Zhili ZHANG, Jin RAO, Tao LIU, Haijun LI, Shuiming LI, Ming LU
  • Publication number: 20230395455
    Abstract: Embodiments of this application provide a semiconductor device, an electronic device, and a semiconductor device preparation method, and relate to the field of chip manufacturing and packaging technologies, to improve heat dissipation efficiency of the semiconductor device without increasing a size. The semiconductor device includes: a substrate, a source, a drain, a gate, and a groove. The source, the drain, and the gate are all formed on the substrate, and an active region is formed between the source and the drain on the substrate. The groove is disposed in the substrate, and a spacing is formed between the groove and the active region. A heat dissipation layer is formed in the groove, and a coefficient of thermal conductivity of the heat dissipation layer is greater than that of the substrate.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 7, 2023
    Inventors: Shuiming LI, Yu WANG, Ping MA, Ming LU, Cen TANG, Zhili ZHANG, Qiang HE, Haijun LI, Tao LIU, Jin RAO
  • Publication number: 20230343835
    Abstract: The technology of this application relates to a high electron mobility transistor including a GaN substrate layer, a barrier layer, a circuit layer, and a field plate that are sequentially stacked. The GaN substrate layer includes a main body layer and a channel layer that are stacked, the channel layer is adjacent to the barrier layer, the circuit layer includes a source, a drain, and a dielectric layer, the dielectric layer is disposed between the source and the drain, the field plate is disposed on a side that is of the dielectric layer and that is away from the barrier layer, an orthographic projection of the field plate on the channel layer is a field plate projection, the channel layer includes a modulation region and a non-modulation region, the non-modulation region surrounds the modulation region, the modulation region and the field plate projection at least partially overlap.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 26, 2023
    Inventors: Zhili ZHANG, Jin RAO, Tao LIU, Haijun LI, Wei LU, Shuiming LI, Cen TANG, Qiang HE, Juncai MA, Chunhua FAN, Yangyi ZHU
  • Publication number: 20230299022
    Abstract: A semiconductor device includes a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and a thickness of the first dielectric layer in a first area is greater than a thickness of the first dielectric layer in a second area outside the first area. The gate is located on the substrate and in the first area, the gate includes a first gate structure and a second gate structure, and the second gate structure is formed on a side of the first dielectric layer that is away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first area and the second area.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Cen TANG, Jin RAO, Tao LIU, Haijun LI, Wei LU, Lingcong LE, Juncai MA, Zhili ZHANG
  • Patent number: 9065406
    Abstract: A continuous variable gain amplifier includes an attenuator network, a boost network, a first amplifying network, and a second amplifying network, where the attenuator network generates first differential output signals according to an input signal and sends the first differential output signals to the first amplifying network and the second amplifying network; the first amplifying network and the second amplifying network receive one output of the first differential output signals each, and generate a first final output signal and a second final output signal respectively according to an externally input control voltage; and the boost network receives the first final output signal and the second final output signal, generates second differential output signals, and sends a first output and a second output of the second differential output signals to the first amplifying network and the second amplifying network, respectively.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 23, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhi Zhang, Xinrong Hu, Jin Rao, Yongli Wang, Xiaosheng Zhu, Rong Peng
  • Patent number: 8907724
    Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 9, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jin Rao, Quan Liu, Yun Zhu, Huajiang Wang
  • Publication number: 20140191803
    Abstract: A continuous variable gain amplifier includes an attenuator network, a boost network, a first amplifying network, and a second amplifying network, where the attenuator network generates first differential output signals according to an input signal and sends the first differential output signals to the first amplifying network and the second amplifying network; the first amplifying network and the second amplifying network receive one output of the first differential output signals each, and generate a first final output signal and a second final output signal respectively according to an externally input control voltage; and the boost network receives the first final output signal and the second final output signal, generates second differential output signals, and sends a first output and a second output of the second differential output signals to the first amplifying network and the second amplifying network, respectively
    Type: Application
    Filed: December 26, 2013
    Publication date: July 10, 2014
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Zhi ZHANG, Xinrong HU, Jin RAO, Yongli WANG, Xiaosheng ZHU, Rong PENG
  • Publication number: 20130314157
    Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 28, 2013
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Jin RAO, Quan LIU, Yun ZHU, Huajiang WANG