Patents by Inventor Jin Ren

Jin Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190269695
    Abstract: Compositions comprising 5-cholesten-3, 25-diol, 3-sulfate (25HC3S) or pharmaceutically acceptable salt thereof and at least one cyclic oligosaccharide, e.g., a cyclodextrin (CD), are provided. The compositions may be used to prevent and/or treat a variety of diseases and conditions, including organ failure (e.g. acute liver failure), high cholesterol/high lipids, and various inflammatory diseases and conditions.
    Type: Application
    Filed: August 1, 2017
    Publication date: September 5, 2019
    Inventors: Shunlin Ren, Leyuan Xu, Yanxia Ning, Jin Koung Kim, WeiQi Lin, Mee Jean Kim, Andrew R. Miksztal, Hongwei Wu, Min L. Lee, Wilma Tamraz
  • Patent number: 10390705
    Abstract: The present invention is directed to a device which includes the following features: a light source illuminates a target to generate an optical inspection signal; a probe head provides an optical path for the optical inspection signal; a probe tube arranged at a front end of the probe head; at least one switched filter module arranged in the optical path, allowing the optical inspection signal to pass therethrough to generate a corresponding spectral signal; and an image sensor arranged behind the switched filter module, receiving the spectral signal and generating a spectral image. The spectral image can be transmitted to an external device, wherefrom the user can use the spectral image to examine the target in further detail. The present invention features a rotary-type or movable-type switched filter module, which facilitates the user to switch filters easily during optical inspection.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 27, 2019
    Assignee: National Chiao Tung University
    Inventors: Mang Ou-Yang, Ting-Wei Huang, Chin-Siang Yang, Yao-Fang Hsieh, Sing-Tsung Li, Jin-Chern Chiou, Ming-Hsui Tsai, Jeng-Ren Duann, Yung-Jiun Lin, Shuen-De Wu, Yung-Jhe Yan, Zheng-Lin He
  • Patent number: 10388531
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 10353011
    Abstract: A system and method for detecting voltage of a battery pack. The system comprises a level transfer circuit array, a multipath data selector, a decoder, a trimming calibration circuit, and an output buffer. The decoder is configured to parse a battery pack cell gating signal; the level transfer circuit array is configured to convert a gated battery pack cell voltage into a common grounded voltage; the multipath data selector is configured to transmit the common grounded voltage, which is converted by the level transfer circuit array, of a battery pack cell to the trimming calibration circuit; the trimming calibration circuit is configured to correct the received common grounded voltage of the battery pack cell; and the output buffer is configured to buffer the common grounded voltage, which is trimmed and calibrated by the trimming calibration circuit, of the battery pack cell.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 16, 2019
    Assignee: CHINA RESOURCES POWTECH (SHANGHAI) CO., LTD.
    Inventors: Yong You, Bingyin Luo, Guocheng Li, Jianmin Li, Linhai Xu, Lei Zhang, Huiyuang Ren, Yujie Wang, Jin Li
  • Publication number: 20190150006
    Abstract: A computer-implemented method for predicting received signal strength in a telecommunication network includes receiving, by one or more processors that execute a convolutional neural network, geographic data representing geographic information of a geographic area and antenna and trasnmit power information of a base station in the geographic area; inputing the geographic data and the antenna and trasnmit power information into the convolutional neural network; predicting received signal strength using the convolutional neural network that includes a number of convolution layers based on the received geographic data and the antenna and trasnmit power information, the received signal strength representing signal strength of wireless signals received at different locations in the geographic area; and outputting the predicted received signal strength.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Jin Yang, Xin Zhang, Jie Ren, Ruilin Liu, Xufeng Chen, Xie Wang, Qitao Song, Lizhou Zhou, Xiujun Shu
  • Publication number: 20190141336
    Abstract: A chip is provided, which includes a first receiving module, a protocol logic module, a color space conversion module, a compression module and a transmitting module. The first receiving module is configured to receive a digital video signal. The protocol logic module is configured to perform protocol unpacking on the digital video signal to obtain a video code stream. The color space conversion module is configured to perform color space conversion on the video code stream. The compression module is configured to perform lossless compression on the video code stream obtained by the color space conversion. The transmitting module is configured to transmit the video code stream obtained by the lossless compression.
    Type: Application
    Filed: May 16, 2018
    Publication date: May 9, 2019
    Inventors: Feng CHEN, Diansheng REN, Hongfeng XIA, Shenghui BAO, Jin SU, Changfang YUE, Wenbo HE
  • Patent number: 10055349
    Abstract: The present disclosure relates to systems, methods, and computer program products for keeping multiple caches updated, or coherent, on multiple servers when the multiple caches contain independent copies of cached data. Example methods may include receiving a request to write data to a block of a first cache associated with a first server in a clustered server environment. The methods may also include identifying a second cache storing a copy of the block, where the second cache is associated with a second server in the clustered environment. The methods may further include transmitting a request to update the second cache with the received write data, and upon receiving a subsequent request to write subsequent data, identifying a third cache for invalidating based on access patterns of the blocks, where the third cache is associated with a third server in the clustered environment.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 21, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jin Ren, Ken Qing Yang, Gregory Evan Fedynyshyn
  • Patent number: 9705819
    Abstract: A device or system includes a plurality of storage resources each associated with a respective performance class, each being associated with selected performance characteristics such as IOPS, bandwidth, etc. The device or system includes a compute instance having access to allocated storage resources, the allocated storage devices including one or more storage resources. The device or system also includes an optimization component adapted to obtain information relating to utilization by the compute instance component of the allocated storage resources, determine that a change to the allocated storage resources is necessary, based on the information, cause data to be migrated from a first storage resource associated with a first performance class to a second storage resource associated with a second storage class, and cause a removal from the allocated storage resources of the first storage resource and an addition to the allocated storage resources of the second storage resource.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 11, 2017
    Assignee: FittedCloud, Inc.
    Inventors: Prakash Manden, Prashant Parikh, Jin Ren, Jienhua Huang
  • Patent number: 9582222
    Abstract: A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 28, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Qing Yang, Jin Ren
  • Patent number: 9524111
    Abstract: A device or system includes a plurality of storage resources each associated with a respective performance class, each being associated with selected performance characteristics such as IOPS, bandwidth, etc. The device or system includes a compute instance having access to allocated storage resources, the allocated storage devices including one or more storage resources. The device or system also includes an optimization component adapted to obtain information relating to utilization by the compute instance component of the allocated storage resources, determine that a change to the allocated storage resources is necessary, based on the information, cause data to be migrated from a first storage resource associated with a first performance class to a second storage resource associated with a second storage class, and cause a removal from the allocated storage resources of the first storage resource and an addition to the allocated storage resources of the second storage resource.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 20, 2016
    Assignee: FittedCloud, Inc.
    Inventors: Prakash Manden, Prashant Parikh, Jin Ren, Jienhua Huang
  • Publication number: 20160210232
    Abstract: The present disclosure relates to systems, methods, and computer program products for keeping multiple caches updated, or coherent, on multiple servers when the multiple caches contain independent copies of cached data. Example methods may include receiving a request to write data to a block of a first cache associated with a first server in a clustered server environment. The methods may also include identifying a second cache storing a copy of the block, where the second cache is associated with a second server in the clustered environment. The methods may further include transmitting a request to update the second cache with the received write data, and upon receiving a subsequent request to write subsequent data, identifying a third cache for invalidating based on access patterns of the blocks, where the third cache is associated with a third server in the clustered environment.
    Type: Application
    Filed: March 25, 2016
    Publication date: July 21, 2016
    Inventors: Jin REN, Ken Qing YANG, Gregory Evan FEDYNYSHYN
  • Patent number: 9298624
    Abstract: The present disclosure relates to systems, methods, and computer program products for keeping multiple caches updated, or coherent, on multiple servers when the multiple caches contain independent copies of cached data. Example methods may include receiving a request to write data to a block of a first cache associated with a first server in a clustered server environment. The methods may also include identifying a second cache storing a copy of the block, where the second cache is associated with a second server in the clustered environment. The methods may further include transmitting a request to update the second cache with the received write data, and upon receiving a subsequent request to write subsequent data, identifying a third cache for invalidating based on access patterns of the blocks, where the third cache is associated with a third server in the clustered environment.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: March 29, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Jin Ren, Ken Qing Yang, Gregory Evan Fedynyshyn
  • Publication number: 20150331794
    Abstract: The present disclosure relates to systems, methods, and computer program products for keeping multiple caches updated, or coherent, on multiple servers when the multiple caches contain independent copies of cached data. Example methods may include receiving a request to write data to a block of a first cache associated with a first server in a clustered server environment. The methods may also include identifying a second cache storing a copy of the block, where the second cache is associated with a second server in the clustered environment. The methods may further include transmitting a request to update the second cache with the received write data, and upon receiving a subsequent request to write subsequent data, identifying a third cache for invalidating based on access patterns of the blocks, where the third cache is associated with a third server in the clustered environment.
    Type: Application
    Filed: May 14, 2014
    Publication date: November 19, 2015
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Jin REN, Ken Qing YANG, Gregory Evan FEDYNYSHYN
  • Publication number: 20150252365
    Abstract: Provided is a method for screening microRNAs with gene silencing function at both transcriptional and post-transcriptional levels. The microRNA obtained via the screening method can down-regulate the expression of mRNA of a target gene by binding to a specific site of 5?-flanking region of the target gene, and also down-regulate the expression of the protein of the target gene by binding to a specific site of the 3?-untranslated region of the target gene. Also provided are microRNAs obtained via the screening method, the use of the same in gene silencing, and a method of gene silencing by using the same.
    Type: Application
    Filed: July 26, 2013
    Publication date: September 10, 2015
    Inventors: Jin Ren, Yizheng Wang, Lingling Miao, Likun Gong, Xinming Qi, Chenggang Li, Guozhen Xing
  • Patent number: 8910875
    Abstract: An indicia reading terminal can comprise an image sensor integrated circuit having a two-dimensional image sensor, a hand held housing encapsulating the two-dimensional image sensor, and an imaging lens configured to focus an image of a target decodable indicia onto the two-dimensional image sensor. The two-dimensional image sensor can include a plurality of pixels arranged in repetitive patterns. Each pattern can include at least one pixel sensitive in a first spectrum region, at least one pixel sensitive in a second spectrum region, and at least one pixel sensitive in a third spectrum region. The image sensor integrated circuit can be configured to capture a frame of image data by reading out a plurality of analog signals. Each read out analog signal can be representative of light incident on a group of two or more pixels of the plurality of pixels.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: December 16, 2014
    Assignee: Metrologic Instruments, Inc.
    Inventors: Jin Ren, Ynjiun Paul Wang, Yong Liu, Timothy Meier, Stephen Patrick Deloge
  • Patent number: 8862842
    Abstract: A data recovery system is disclosed that permits recovery of data in a computer memory. The system includes an update storage system, a long-term storage system, a coupling functional circuit, and a parity register. The update storage system is for providing backup storage of recently updated data. The long-term storage system is for providing backup storage of data that has not been recently updated. The coupling functional circuit is for providing a bit-wise commutative binary operation of data from the update storage system and from the long term storage system. The parity register is for maintaining parity snapshots of the output of the coupling functional circuit.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: October 14, 2014
    Assignee: Rhode Island Board of Education , State of Rhode Island and Providence Plantations
    Inventors: Qing K. Yang, Weijun Xiao, Jin Ren
  • Publication number: 20140188811
    Abstract: A system and method are disclosed for providing continuous file protection in a computer processing system. In accordance with an embodiment, the system includes a configuration module, a filter driver, and a storage module. The configuration module permits a user to elect certain files or folders for protection. The configuration module runs at an application layer without involving the computer processing system's operating system. The filter driver intercepts and splits write input and outputs addressed at protected files or folders. The storage module is also run without involving the computer processing system's operating system. The storage module is for performing functions including data logging, version managements, and data recovery.
    Type: Application
    Filed: February 24, 2014
    Publication date: July 3, 2014
    Applicant: Board of Governors for Higher Education, State of Rhode Island and Providence Plantations
    Inventors: Qing K. Yang, Jin Ren
  • Patent number: 8722538
    Abstract: A method for forming a contact window includes: a step of providing a substrate; a step of forming a patterned amorphous carbon layer or spin-on coating layer, in which a surface of the substrate is exposed at two sides of the amorphous carbon layer or spin-on coating layer; a step of forming an interlayer dielectric layer on the substrate; a step of removing a portion of the interlayer dielectric layer until the patterned amorphous carbon layer or spin-on coating layer is exposed; a step of removing the patterned amorphous carbon layer or spin-on coating layer to form an opening; and a step of filling the opening with a conductive material to form the contact window.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 13, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Jung-Yuan Hsieh, Shih-Hsi Chen, Jin-Ren Han
  • Publication number: 20140011357
    Abstract: A method for forming a contact window includes: a step of providing a substrate; a step of forming a patterned amorphous carbon layer or spin-on coating layer, in which a surface of the substrate is exposed at two sides of the amorphous carbon layer or spin-on coating layer; a step of forming an interlayer dielectric layer on the substrate; a step of removing a portion of the interlayer dielectric layer until the patterned amorphous carbon layer or spin-on coating layer is exposed; a step of removing the patterned amorphous carbon layer or spin-on coating layer to form an opening; and a step of filling the opening with a conductive material to form the contact window.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 9, 2014
    Applicant: POWERCHIP TECHNOLOGY CORPORATION
    Inventors: Jung-Yuan Hsieh, Shih-Hsi Chen, Jin-Ren Han
  • Publication number: 20120144099
    Abstract: A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.
    Type: Application
    Filed: February 7, 2012
    Publication date: June 7, 2012
    Applicant: VELOBIT, INC.
    Inventors: Qing Yang, Jin Ren