Abstract: Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

Abstract: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) structure having a cylindrical shape. Elements of the MTJ structure are co-axial. The MTJ structure includes a conductive layer, an insulating layer co-axially formed around the conductive layer and a material layer formed around the insulating layer, the material layer being co-axial with the conductive layer and having a plurality of magnetic layers. The material layer includes a lower magnetic layer, a tunneling layer, and an upper magnetic layer that are sequentially stacked around and along the conductive layer.

Abstract: Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

Abstract: Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, and a work function of the metal gate is determined according to ratios of the metal nitride with respect to the metal carbide.

Abstract: Provided are a phase change layer and a method of forming the phase change layer and a phase change memory device including the phase change layer, and methods of manufacturing and operating the phase change memory device. The phase change layer may be formed of a quaternary compound including an amount of indium (In) ranging from about 15 at. % to about 20 at. %. The phase change layer may be InaGebSbcTed, wherein an amount of germanium (Ge) ranges from about 10 at. %?b?about 15 at. %, an amount of antimony (Sb) ranges from about 20 at. %?c?about 25 at. %, and an amount of tellurium (Te) ranges from about 40 at. %?d?about 55 at. %.

Abstract: A phase change memory device includes a substrate, a switching element formed in the substrate and a storage node connected to the switching element. The storage node may include a lower electrode connected to the switching element, a first phase change layer formed on the lower electrode, a magnetic resistance layer formed on the first phase change layer, a second phase change layer formed on the magnetic resistance layer and an upper electrode formed on the second phase change layer.

Abstract: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.

Abstract: A storage node, a phase change random access memory having an improved structure to improve adhesion of a phase change material layer and methods of fabricating the same are provided. The storage node may include a bottom electrode, a top electrode, a phase change material layer inserted between the bottom electrode and the top electrode, and an adhesion interfacial layer inserted between the bottom electrode and the phase change material layer. The phase change random access memory may include a switching device and the storage node connected to the switching device.

Abstract: A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.

Abstract: A phase change RAM (PRAM) including a resistance element having a diode function, and methods of fabricating and operating the same are provided. The PRAM may include a substrate, a phase change diode layer formed on the substrate and an upper electrode formed on the phase change diode layer. The phase change diode layer may include a material layer doped with first impurities, and a phase change layer which is stacked on the doped layer. The phase change layer may show characteristics of a semiconductor material doped with impurities having an opposite conductive type to that of the first impurities.

Abstract: A phase change memory device includes a switch and a storage node connected to the switch. The storage node includes a first electrode, a phase change layer and a second electrode. The phase change layer is formed of an InSbTe compound doped with Ge. In a method of operating a phase change memory including a switch and a storage node, the switch is maintained in an on state, and a first current is applied to the storage node.

Abstract: A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Abstract: A phase change memory device includes a substrate, a switching element formed in the substrate and a storage node connected to the switching element. The storage node may include a lower electrode connected to the switching element, a first phase change layer formed on the lower electrode, a magnetic resistance layer formed on the first phase change layer, a second phase change layer formed on the magnetic resistance layer and an upper electrode formed on the second phase change layer.

Abstract: A phase change random access memory (PRAM), and a method of operating the PRAM are provided. In the PRAM comprising a switching element and a storage node connected to the switching element, the storage node comprises a first electrode, a second electrode, a phase change layer between the first electrode and a second electrode, and a heat efficiency improving element formed between the first electrode and the phase change layer. The heat efficiency improving element may be one of a carbon nanotube (CNT) layer, a nanoparticle layer, and a nanodot layer, and the nanoparticle layer may be a fullerene layer.

Abstract: A phase change material, a PRAM including the same, and methods of manufacturing and operating the same are provided. Insulating impurities may be uniformly distributed over an entire or partial region of the phase change material. The PRAM may include a phase change layer including the phase change material. The insulating impurity content of the phase change material may be 0.1 to 10% (inclusive) the volume of the phase change material. The insulating impurity content of the phase change material may be adjusted by controlling the power applied to a target including the insulating impurities.

Abstract: In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film.

Abstract: A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.

Abstract: Provided is a method of operating a phase change random access memory comprising a switching device and a storage node comprising a phase change layer. The method includes applying a reset current passing through the phase change layer from a lower portion of the phase change layer toward an upper portion of the phase change layer and being smaller than 1.6 mA to the storage node to change a portion of the phase change layer into an amorphous state. The set voltage is in an opposite direction is exemplary embodiments, and a connector is of small cross-sectional area.

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) structure having a cylindrical shape. Elements of the MTJ structure are co-axial. The MTJ structure includes a conductive layer, an insulating layer co-axially formed around the conductive layer and a material layer formed around the insulating layer, the material layer being co-axial with the conductive layer and having a plurality of magnetic layers. The material layer includes a lower magnetic layer, a tunneling layer, and an upper magnetic layer that are sequentially stacked around and along the conductive layer.