Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area.

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area.

Abstract: A package according to the invention comprises at least two integrated circuit (IC) chips encapsulated therein. Each of the IC chips has its option pad, and the option pads of the IC chips are biased, at the package level, to different logic levels so as to distinguish between the IC chips. Particularly, the chips of the present invention have identical address coding scheme and are each comprised of a memory cell array for storing data; a command register for activating one of master signals each indicative of a read mode, a program mode and an erase mode in response to an externally applied command; and a chip disable circuit coupled to a corresponding option pad, for determining whether or not a corresponding semiconductor memory device is selected, and for resetting the command register so as to disable the activated master signal when the corresponding semiconductor memory device is unselected.

Abstract: A semiconductor memory includes a plurality of memory cells being electrically programmed and coupled to word lines and bit lines. A first latch circuit holds data during a programming operation including a verifying step. A second latch circuit generates a result from verifying a programmed memory cell, in response to the data held in the first latch circuit.

Abstract: A semiconductor memory is disclosed having lockable cells which can be programmed or erased to store the information of an erasure lock or an erasure unlock without disturbing data stored in memory cells. The memory includes a memory cell array formed of a plurality of blocks, the blocks formed of a plurality of memory cells which are coupled to a plurality of memory word lines and bit lines, a lockable cell array formed of a plurality of lockable cells which are coupled to a lockable bit line and a plurality of lockable word lines which are electrically isolated from the memory word lines, and a lockable decoding circuit to generate a plurality of decoding signals to select the lockable word lines independent upon a selection of the memory word lines.