Patents by Inventor Jin-seong Heo

Jin-seong Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9525076
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho Lee, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jin-seong Heo
  • Patent number: 9515144
    Abstract: Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to the substrate, a gate insulating layer that covers one side surface of the graphene channel layer, a gate electrode on the gate insulating layer, and a source electrode and a drain electrode that are formed separately from each other on other side surface of the graphene channel layer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Jaeho Lee, Jin-seong Heo, Kiyoung Lee
  • Patent number: 9455256
    Abstract: Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Hyeon-jin Shin
  • Patent number: 9373685
    Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: June 21, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-jin Shin, Kyung-eun Byun, Hyun-jae Song, Seong-jun Park, David Seo, Yun-sung Woo, Dong-wook Lee, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo, In-kyeong Yoo
  • Patent number: 9359211
    Abstract: Methods of fabricating graphene using an alloy catalyst may include forming an alloy catalyst layer including nickel on a substrate and forming a graphene layer by supplying hydrocarbon gas onto the alloy catalyst layer. The alloy catalyst layer may include nickel and at least one selected from the group consisting of copper, platinum, iron and gold. When the graphene is fabricated, a catalyst metal that reduces solubility of carbon in Ni may be used together with Ni in the alloy catalyst layer. An amount of carbon that is dissolved may be adjusted and a uniform graphene monolayer may be fabricated.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-sung Woo, David Seo, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo
  • Patent number: 9349802
    Abstract: Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Hyeon-jin Shin, Jae-ho Lee
  • Patent number: 9306021
    Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-jong Chung, David Seo, Seong-jun Park, Kyung-eun Byun, Hyun-jae Song, Hee-jun Yang, Jin-seong Heo
  • Patent number: 9306005
    Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-eun Byun, Seong-jun Park, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9299789
    Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: David Seo, Ho-jung Kim, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, Hyun-jae Song, Jin-seong Heo
  • Patent number: 9281404
    Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hee-jun Yang, Hyun-jong Chung
  • Patent number: 9257528
    Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong Chung, Jin-seong Heo, Hee-jun Yang, Sun-ae Seo, Sung-hoon Lee
  • Patent number: 9184236
    Abstract: A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Seo, Jin-seong Heo, Hyun-jong Chung, Hee-jun Yang, Seong-jun Park, Hyun-jae Song
  • Patent number: 9166062
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 20, 2015
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9142635
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Patent number: 9136336
    Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Hyun-jong Chung, Hyun-jae Song, Hee-jun Yang, David Seo
  • Patent number: 9108848
    Abstract: Example embodiments relate to methods of manufacturing and transferring a larger-sized graphene layer. A method of transferring a larger-sized graphene layer may include forming a graphene layer, a protection layer, and an adhesive layer on a substrate and removing the substrate. The graphene layer may be disposed on a transferring substrate by sliding the graphene layer onto the transferring substrate.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 18, 2015
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation For Corporate Collaboration
    Inventors: Yun-sung Woo, David Seo, Su-kang Bae, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo, Myung-hee Jung
  • Publication number: 20150228804
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 13, 2015
    Applicant: Seoul National University R&DB Foundation
    Inventors: Jae-ho LEE, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Hyung-cheol SHIN, Jae-hong LEE, Hyun-jong CHUNG, Jin-seong HEO
  • Patent number: 9105556
    Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung
  • Patent number: 9093509
    Abstract: A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seong Heo, Sun-ae Seo, Sung-hoon Lee, Hyun-jong Chung, Hee-jun Yang
  • Patent number: 9064777
    Abstract: According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Seong Heo, Hyun-jong Chung, Hyun-jae Song, Seong-jun Park, David Seo, Hee-jun Yang