Patents by Inventor Jin Seong Lee

Jin Seong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200042795
    Abstract: Disclosed is a mobile terminal for providing information based on an image, wherein the mobile terminal executes at least one of an installed artificial intelligence (AI) algorithm and a machine learning algorithm, and is capable of communicating with other electronic devices and external servers in a 5G communication environment. The mobile terminal includes a camera, a display, and a processor. Accordingly, since an image capture target can be accurately recognized, various services for improving user convenience can be provided.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicant: LG ELECTRONICS INC.
    Inventors: Eun Sang LEE, Hye Young KOO, In Suk KIM, Jin Seong LEE
  • Patent number: 10522550
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Publication number: 20190359812
    Abstract: A thermoplastic resin composition and a molded article produced using the same.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 28, 2019
    Inventors: Jin Seong LEE, Gi Sun KIM, Hyun Ji OH, Young Chul KWON, Hyun Taek JEONG
  • Publication number: 20190267386
    Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Hyun-Jung Lee, Dongsoo Woo, Jin-Seong Lee, Namho Jeon, Jaeho Hong
  • Patent number: 10312243
    Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-jung Lee, Dongsoo Woo, Jin-Seong Lee, Namho Jeon, Jaeho Hong
  • Publication number: 20190115351
    Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: April 18, 2019
    Inventors: NAMHO JEON, Jin-Seong LEE, Hyun-jung LEE, Dongsoo Woo, Donggyu HEO, Jaeho Hong
  • Patent number: 10242293
    Abstract: Provided are a method and program for computing a bone age using a deep neural network. The method for computing a bone age using a deep neural network, including: receiving an analysis target image that is a specific medical image to compute the bone age; and analyzing the analysis target image by at least one computer using the deep neural network to compute the bone age. According to the present disclosure, since the bone age is computed by accumulating medical images of a specific race (particularly, Korean) and analyzing the same, it is possible to compute an accurate bone age that conforms to race.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 26, 2019
    Assignees: The Asan Foundation, Vuno, Inc.
    Inventors: Woo Hyun Shim, Jin Seong Lee, Yu Sub Sung, Hee Mang Yoon, Jung Hwan Baek, Sang Ki Kim, Hyun Jun Kim, Ye Ha Lee, Kyu Hwan Jung
  • Publication number: 20190088659
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 21, 2019
    Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
  • Publication number: 20190027480
    Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.
    Type: Application
    Filed: March 14, 2018
    Publication date: January 24, 2019
    Inventors: Hyun-jung Lee, Dongsoo Woo, Jin-Seong Lee, Namho Jeon, Jaeho Hong
  • Patent number: 10141316
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Publication number: 20180232603
    Abstract: Provided are a method and program for computing a bone age using a deep neural network. The method for computing a bone age using a deep neural network, including: receiving an analysis target image that is a specific medical image to compute the bone age; and analyzing the analysis target image by at least one computer using the deep neural network to compute the bone age. According to the present disclosure, since the bone age is computed by accumulating medical images of a specific race (particularly, Korean) and analyzing the same, it is possible to compute an accurate bone age that conforms to race.
    Type: Application
    Filed: December 30, 2015
    Publication date: August 16, 2018
    Inventors: Woo Hyun Shim, Jin Seong Lee, Yu Sub Sung, Hee Mang Yoon, Jung Hwan Baek, Sang Ki Kim, Hyun Jun Kim, Ye Ha Lee, Kyu Hwan Jung
  • Publication number: 20180175016
    Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 21, 2018
    Inventors: Tae Sun Kim, Hyun Jae Kang, Tae Hoi Park, Jin Seong Lee, Eun Sol Choi, Min Keun Kwak, Byung Kap Kim, Sung Won Choi
  • Publication number: 20170200725
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Application
    Filed: September 26, 2016
    Publication date: July 13, 2017
    Inventors: Ki Seok LEE, Jeong Seop SHIM, Mi Na LEE, Augustin Jinwoo HONG, Je Min PARK, Hye Jin SEONG, Seung Min OH, Do Yeong LEE, Ji Seung LEE, Jin Seong LEE
  • Patent number: 9587058
    Abstract: A resin composition includes a phosphorus-based acrylic copolymer (A) including (a1) an acrylic monomer represented by Formula 1 and (a2) a phosphorus-based acrylic monomer represented by Formula 2 as defined in the specification. The resin composition can have flame retardancy, heat resistance, mechanical properties, and/or flowability, while maintaining properties of high transparency and scratch resistance.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 7, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Kee Hae Kwon, Jin Hwa Chung, Jin Seong Lee, Man Suk Kim, Kwang Soo Park, Ja Kwan Koo
  • Patent number: 9340670
    Abstract: The present invention relates to an environmentally friendly flame-retardant polycarbonate resin composition having scratch resistance, which includes a specific (meth)acrylic flame-retardant copolymer to improve flame retardancy and scratch resistance.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 17, 2016
    Assignee: Cheil Industries Inc.
    Inventors: Jin Hwa Chung, Ja Kwan Koo, Joo Hyun Jang, Yong Hee Kang, Kee Hae Kwon, Kwang Soo Park, Man Suk Kim, Jin Seong Lee
  • Publication number: 20160125402
    Abstract: Methods and devices for payment using token are provided, one of methods comprises, receiving a public key and a payment device token from a payment device, creating a digital signature through encryption of the payment device token and a stored user token using the public key, and payment request data including the digital signature, transmitting the payment request data to the payment device and updating the user token through performing of a token update operation.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Jin Seong LEE, Hee Jin PARK, Seung Hyun LEE, Weon Young YOUN, Tae Hun KIM
  • Patent number: 9127157
    Abstract: The present invention provides a flame-retardant and scratch-resistant polycarbonate resin composition including a (meth)acrylic flame-retardant copolymer.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: September 8, 2015
    Assignee: Cheil Industries Inc.
    Inventors: Jin Hwa Chung, Kee Hae Kwon, Jin Seong Lee, Man Suk Kim, Yong Hee Kang, Kwang Soo Park, Ja Kwan Koo
  • Patent number: 9075401
    Abstract: A method of correcting a sensor that detects a detection object and generates a detection signal includes: determining a homing-signal generation time difference between points of time when the detection signal is generated according to a direction in which the detection object enters the sensor and correcting a homing-signal generation time by using the determined homing-signal generation time difference.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG TECHWIN CO., LTD.
    Inventor: Jin-Seong Lee
  • Publication number: 20150125050
    Abstract: Disclosed is a fingerprint recognition sensor module including a flexible printed circuit board. The flexible printed circuit board includes a first sensing region formed with a first sensing input unit, a second sensing region formed with a second sensing input unit, a chip mounting region on which an ASIC is mounted to convert a fingerprint sensed through the input units into a digital signal and transmit the digital signal to a connector, and a connection section to which the connector is connected. The chip mounting region and the first and second sensing regions are separated from each other on the same surface, and the flexible printed circuit board is folded such that projection planes of the chip mounting region and the first and second sensing regions are superposed one above another.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jin-Seong LEE, Jong-Hwa KIM, Kyoung-Jun PARK, Ho-Chul JOUNG, Young-Ho KIM
  • Patent number: 8969444
    Abstract: A polycarbonate resin composition includes (A) about 90 to about 97% by weight of a rubber-reinforced polystyrene resin, (B) about 3 to about 10% by weight of a polyphenylene ether resin, (C) about 10 to about 20 parts by weight of a halogen compound including a triazine group, or a mixture of a halogen compound including a triazine group and a diphenyl ethane bromide compound based on about 100 parts by weight of a base resin comprising (A) and (B), and (D) about 0.01 to about 3 parts by weight of an antimony compound based on about 100 parts by weight of the base resin comprising (A) and (B). The composition can exhibit excellent flame retardancy, colorability and injection molding thermal stability.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 3, 2015
    Assignee: Cheil Industries Inc.
    Inventors: Jin Seong Lee, Gyeong Ha Chae, Young Chul Kwon, Kang Yeol Park