Abstract: The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

Abstract: A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.

Abstract: According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply.

Abstract: A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.

Abstract: A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.

Abstract: A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.

Abstract: According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply.

Abstract: An objective optical system for aberration correction and an optical head adopting the objective optical system are provided. The objective optical system includes a diffraction lens and a refractive lens. The diffraction lens converges incident light and corrects aberration. The refractive lens focuses light transmitted by the diffraction lens on an optical disk. Contamination and damage of the diffraction lens are prevented, and light receiving efficiency is improved.

Abstract: In a burst operation, a counter (18) receives one or more bits of a starting column address. The count signal (A[2:1]) generated by the counter is provided to an address adder (20). The address adder generates column address bits (B[2:1]) for a column to be selected in the burst operation. The Y-decoder circuitry (16.0,16.1) selects an even column and an odd column in parallel. The count address bits (A[2:1]) are used as address bits for the even column, and the address bits (B[2:1]) generated by the address adder are used as address bits for the odd column, or vice versa. The even and odd columns can be at non-consecutive column addresses, or they can be at consecutive column addresses starting at an odd column address boundary. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories. Some embodiments are suitable for double data rate memories.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: A sense amplifier enable signal generator for a semiconductor memory device, comprising a counter for generating a pulse signal synchronously with a clock signal when a row address strobe bar signal is made active and suppressing the generation of the pulse signal when the row address strobe bar signal is disabled, and a comparator for generating a sense amplifier enable signal when an output value from the counter reaches a predetermined time delay value and suppressing the generation of the sense amplifier enable signal when the row address strobe bar signal is disabled. According to the present invention, a sense amplifier can be operated at a proper time without being affected by a process parameter, an operating voltage, temperature, etc.

Abstract: A memory device does not operate an input/output sense-amplifier corresponding to a row to be refreshed, thus prevents a data mixing between a row of an active state and another row to be refreshed, thereby performing a refresh operation under an active mode. In addition, if the block of a row to be refreshed is not identical with other block of a row placed at an active state, the memory device performs a refresh operation under an active mode, thereby increasing an effective bandwidth of DRAM.

Abstract: An optical disc player is mounted to a frame by a vibration damping mechanism filled with a mixture of silicone oil and silica. The silicone oil has a viscosity in the range of 50,000 to 250,000 centistokes, and is 95 to 70% of the mixture weight. The silica has a viscosity in the range of 50,000 to 150,000 centistokes and is 5 to 30% of the mixture weight.

Abstract: A device for damping vibrations or shocks in an optical disk player has an external housing; a deck housing located in the external housing, each of two side walls of the deck housing having a plurality of holes; at least a pair of support brackets attached to the external housing to maintain a specified space against each side wall of the deck housing, each support bracket having a plurality of holes corresponding to the holes in the two side walls of the deck housing; and, a plurality of vibrations damping members for damping vibration, the vibrations damping members formed of an elastic material, and inserted between each of the corresponding holes in the deck housing and support brackets. The vibrations damping member is formed by an elastic container with fluid to the extent that the internal pressure of the container exceeds the standard atmospheric pressure.