Patents by Inventor Jinsheng Gao
Jinsheng Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240091334Abstract: The present disclosure provides a combined vaccine against human respiratory syncytial virus (RSV) infection and a method thereof for inducing immune response. The combined vaccine includes; a first composition including an immunologically effective dosage of a replication-deficient human adenovirus type 26 vector contains a nucleotide encoding an antigenic protein of RSV and a pharmaceutically acceptable vector; and a second composition including an immunologically effective dosage of a replication-deficient chimpanzee adenovirus type 63 vector contains a nucleotide encoding an antigenic protein of RSV and a pharmaceutically acceptable vector. The first composition is a primary immunization composition and the second composition is a booster immunization composition, or vice versa. In the present disclosure, the combined vaccine is used for inducing a protective immunity against RSV infection, and a method is provided for generating the protective immunity against RSV infection.Type: ApplicationFiled: August 11, 2021Publication date: March 21, 2024Inventors: Jinsheng HE, Lin DU, Yuanhui FU, Weihua ZHU, Xianglei PENG, Bo GAO, Yanpeng ZHENG, Meiqin LIU
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Publication number: 20230159583Abstract: The present invention relates to a compound for treating gout, a preparation method therefor and the use thereof. The compound is as represented by formula I. Disclosed in the present invention are a method for preparing the compound and the use of the compound in the preparation of a drug for treating or preventing gout. Further disclosed in the present invention is a composition product containing the compound. The compound provided by the present invention can be used for treating inflammation and gout, and can also be used for treating cancers.Type: ApplicationFiled: March 18, 2021Publication date: May 25, 2023Applicant: Huazhong Pharmaceutical Co., Ltd.Inventors: Qingsong Li, Linshan Yao, Jinsheng Gao, Fei Yuan, Lei Chen, Hongyang Zhang
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Publication number: 20220260495Abstract: The present disclosure belongs to the field of application of protein, and relates to use of a protein in predicting properties of a drug. The drug comprises pesticides, human drugs and veterinary drugs, and the protein is applied in the following steps: preparing a 0.02 M phosphate buffer solution with pH value of 7.4; dissolving and diluting a protein solution with the prepared buffer solution according to a signal value to obtain a protein diluent; mixing the prepared protein diluent with the drug to be tested in a molar ratio of 1: (1-300) to obtain a mixed solution to be tested, and predicting the drug properties by using fluorescence spectrum, synchronous fluorescence, three-dimensional fluorescence, circular dichroism spectrum, UV-Vis absorption spectrum, linear spectrum or band spectrum.Type: ApplicationFiled: December 6, 2021Publication date: August 18, 2022Inventors: Hongliang XU, Qin ZHOU, Li LI, Zishi WANG, Xiangshuai LI, Yue XING, Jinsheng GAO
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Patent number: 11349013Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.Type: GrantFiled: August 23, 2019Date of Patent: May 31, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Haigou Huang, Xusheng Wu, Jinsheng Gao
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Patent number: 10930549Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: September 17, 2019Date of Patent: February 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Patent number: 10644156Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.Type: GrantFiled: March 12, 2018Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang
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Patent number: 10559470Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.Type: GrantFiled: January 22, 2018Date of Patent: February 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Haigou Huang, Jinsheng Gao, Hong Yu, Jinping Liu, Huang Liu
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Publication number: 20200013672Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Jinsheng GAO, Daniel JAEGER, Chih-Chiang CHANG, Michael AQUILINO, Patrick CARPENTER, Junsic HONG, Mitchell RUTKOWSKI, Haigou HUANG, Huy CAO
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Patent number: 10522639Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: June 29, 2019Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Publication number: 20190378914Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.Type: ApplicationFiled: August 23, 2019Publication date: December 12, 2019Inventors: Haigou Huang, Xusheng Wu, Jinsheng Gao
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Patent number: 10483369Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.Type: GrantFiled: October 30, 2017Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Haigou Huang, Xusheng Wu, Jinsheng Gao
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Patent number: 10460986Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Publication number: 20190326416Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate electrode is arranged in a lower portion of a trench in an interlayer dielectric layer, and a liner is formed inside an upper portion of the trench and over a top surface of the interlayer dielectric layer. A dielectric material is deposited in in the upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Haigou Huang, Jiehui Shu, Chih-Chiang Chang, Xingzhao Shi, Jinsheng Gao, Huy Cao
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Publication number: 20190326408Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10418455Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: September 26, 2017Date of Patent: September 17, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Publication number: 20190280114Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.Type: ApplicationFiled: March 12, 2018Publication date: September 12, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang
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Patent number: 10388562Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.Type: GrantFiled: August 16, 2017Date of Patent: August 20, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Haigou Huang, Daniel Jaeger, Xusheng Wu, Jinsheng Gao
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Publication number: 20190237363Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Inventors: Jinsheng GAO, Daniel JAEGER, Chih-Chiang CHANG, Michael AQUILINO, Patrick CARPENTER, Junsic HONG, Mitchell RUTKOWSKI, Haigou HUANG, Huy CAO
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Publication number: 20190228976Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.Type: ApplicationFiled: January 22, 2018Publication date: July 25, 2019Inventors: Haigou HUANG, Jinsheng GAO, Hong YU, Jinping LIU, Huang LIU
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Patent number: 10340142Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.Type: GrantFiled: March 12, 2018Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Jiehui Shu, Pei Liu, Jinping Liu