Abstract: A video signal processing method applied for a TV system is disclosed. In this method, the received video signal is processed by a video decoding process, and then the decoded video signal is processed by a de-interlacing process. A still or corresponsively still image signal is generated and blended with the de-interlaced video signal to generate a blended signal which is displayed to make sure the OSD information can always be shown at the top layer of the screen of the LCD panel.

Abstract: A video processing method and a device thereof are described. The method includes the steps as follows. An input video signal is received, in which a single period of the input video signal has a plurality of first input frames and a plurality of second input frames. The input video signal is processed, so as to generate an output video signal, in which a single period of the output video signal has a plurality of first output frames and a plurality of second output frames, and an amount of the first output frames is the same as an amount of the second output frames. A sum of the amount of the first output frames and the amount of second output frames is an integer multiple of a sum of an amount of the first input frames and an amount of the second input frames.

Abstract: A video system includes a decoder and a scaler. The decoder tracks a video signal, generates a synchronization signal and a frequency offset signal, decodes the video signal, and outputs a decoded signal in accordance with the synchronization signal. The scaler generates a frequency control signal in accordance with the frequency drift signal, generates an output clock signal in accordance with the frequency control signal, generates a scaled signal in accordance with the decoded signal, and outputs a display signal in accordance with the scaled signal and the output clock signal.

Abstract: An image-scaling-down method for scaling down a pixel block of an image component is provided. The pixel block includes a plurality of sub-blocks and each sub-block includes m number of non-processed pixel data where m is a positive integer. The image-scaling-down method comprises: determining a scaling down factor wherein m divided by n is the scaling down factor and n is a positive integer less than m; and calculating n number of processed pixel data in each sub-block by using the scaling down factor and the m number of the non-processed pixel data, wherein the combination of the n number of the processed pixel data of the sub-blocks corresponds to the image component.

Abstract: A video processing apparatus for de-interlacing includes a video decoder and a de-interlacing circuit. The video decoder decodes a video data stream to generate an interlaced video signal and transmits a first interlaced control signal. The de-interlacing circuit is coupled to the video decoder, and includes a detecting unit and an interlacing to progressive converting unit. The detecting unit generates a second interlaced control signal according to the interlaced video signal and the first interlaced control signal. The interlacing to progressive converting unit is coupled to the detecting unit for receiving the interlaced video signal as well as the second interlaced control signal and for converting the interlaced video signal into a first progressive video signal according to the second interlaced control signal.

Abstract: A method for decoding a video block in a video picture includes: selecting N motion vectors from M motion vector, wherein the M motion vectors corresponding to at least a video block of at least a reference area; and decoding the video block according to the N motion vectors.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: An image processing system, for processing display data and vertical blanking interval data carried by a composite signal, is disclosed. The image process system includes: a video decoder, for decoding the display data to generate corresponding image data; a VBI decoder, for decoding the VBI data to generate corresponding VBI image data; a converter, for converting the VBI image data into color index data; a transmission interface, for transmitting the decoded image data and color index data; and an image processing module, for receiving the image data and the color index data to deinterlace/scale the image data and converting the color index data back into the original VBI image data, mixing the processed image data and the VBI image data such that data to be displayed can be generated.

Abstract: A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.

Abstract: An apparatus for image adjustment and an associated method are disclosed. The apparatus can determine an adjusted value of a pixel in an image frame by comparing the pixel and a correspondingly located pixel in a previous image frame. When there is much image variation, an adjustment is made for each pixel in an original image frame for display, thereby providing better visual effects.

Abstract: A video processing apparatus for de-interlacing includes a video decoder and a de-interlacing circuit. The video decoder decodes a video data stream to generate an interlaced video signal and transmits a first interlaced control signal. The de-interlacing circuit is coupled to the video decoder, and includes a detecting unit and an interlacing to progressive converting unit. The detecting unit generates a second interlaced control signal according to the interlaced video signal and the first interlaced control signal. The interlacing to progressive converting unit is coupled to the detecting unit for receiving the interlaced video signal as well as the second interlaced control signal and for converting the interlaced video signal into a first progressive video signal according to the second interlaced control signal.

Abstract: An image-scaling-down method for scaling down a pixel block of an image component is provided. The pixel block includes a plurality of sub-blocks and each sub-block includes m number of non-processed pixel data where m is a positive integer. The image-scaling-down method comprises: determining a scaling down factor wherein m divided by n is the scaling down factor and n is a positive integer less than m; and calculating n number of processed pixel data in each sub-block by using the scaling down factor and the m number of the non-processed pixel data, wherein the combination of the n number of the processed pixel data of the sub-blocks corresponds to the image component.

Abstract: A source frame signal received at a first frame rate is converted to a destination frame signal output at a second frame rate. By adjusting the clock frequency of the clock signal in the destination frame signal, the second frame rate is made to be the same as the first frame rate. Adjusting the destination clock frequency prevents overflow and underflow conditions. The destination clock frequency is decreased to prevent underflow or increased to prevent overflow. The destination clock frequency during the last horizontal line is adjusted to comply with some display devices having a maximum time constraint from a last horizontal sync signal to a vertical sync signal in the destination frame signal.

Abstract: An image displaying method for a television includes: selecting a portion of a plurality of display regions of a screen of the television to display a still or animated image when a power-on signal is received; and utilizing all the plurality of display regions to display images corresponding to a television signal after a predetermined time period beginning from when the power-on signal is received. The present invention further discloses an image displaying method for a television, including: selecting a portion of a plurality of display regions of a screen of the television and stopping the displaying of images corresponding to a television signal on the selected display regions when a power-off signal is received; and stopping the displaying of images corresponding to the television signal on all the plurality of display regions after a predetermined time period beginning from when the power-off signal is received.

Abstract: A video processing method and a device thereof are described. The method includes the steps as follows. An input video signal is received, in which a single period of the input video signal has a plurality of first input frames and a plurality of second input frames. The input video signal is processed, so as to generate an output video signal, in which a single period of the output video signal has a plurality of first output frames and a plurality of second output frames, and an amount of the first output frames is the same as an amount of the second output frames. A sum of the amount of the first output frames and the amount of second output frames is an integer multiple of a sum of an amount of the first input frames and an amount of the second input frames.

Abstract: A video system includes a decoder and a scaler. The decoder tracks a video signal, generates a synchronization signal and a frequency offset signal, decodes the video signal, and outputs a decoded signal in accordance with the synchronization signal. The scaler generates a frequency control signal in accordance with the frequency drift signal, generates an output clock signal in accordance with the frequency control signal, generates a scaled signal in accordance with the decoded signal, and outputs a display signal in accordance with the scaled signal and the output clock signal.

Abstract: An image processing circuit for processing a video signal includes: a separator for separating the video signal into a brightness signal and a color signal; a first filter coupled to the separator for filtering the color signal; and a second filter coupled to the separator for filtering the brightness signal.

Abstract: A method for converting a frame rate of a video signal comprising a data enable signal by means of a first buffer and a second buffer is disclosed. The method comprises: alternatively accessing the first buffer and the second buffer according to a first frame rate; determining an accessing time point of the first and the second buffers according to the data enable signal; and accessing the buffer, which is one of the first and the second buffers and not accessed at the accessing time point, according to a second frame rate, wherein the second frame rate is faster than the first frame rate.

Abstract: A method for decoding a video block in a video picture includes: selecting N motion vectors from M motion vector, wherein the M motion vectors corresponding to at least a video block of at least a reference area; and decoding the video block according to the N motion vectors.

Abstract: A method of transmitting data by inserting audio information for use within a video editing apparatus includes encoding at least one analog audio signal into digital audio channel information according to an encoding format, the digital audio channel information including a length element and an audio encoded element; utilizing at least a first noise bit to replace at least one bit from within the length element to thereby generate a replacement length element; utilizing at least a second noise bit to replace at least one bit from the audio encoded element to thereby generate a replacement audio encoded element; generating replacement audio channel information according to the replacement length element and the corresponding replacement audio encoded element; according to all the replacement audio channel information generating a replacement digital audio sample; and inserting the replacement digital audio sample into a blanking section of transmitted data.