Patents by Inventor Jin-Sheng Yang

Jin-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7727903
    Abstract: A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 1, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Huo-Tieh Lu, Jin-sheng Yang, Pei-Lin Kuo
  • Publication number: 20090111272
    Abstract: A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Huo-Tieh Lu, Jin-sheng Yang, Pei-Lin Kuo
  • Publication number: 20070066031
    Abstract: A method of manufacturing a semiconductor structure for a substrate having electronic elements formed thereon is described. The method includes steps of forming a dielectric layer over the substrate and forming a trench in the dielectric layer. It should be noticed that a border shape of the trench is a non-straight shape. Finally, the trench is filled with a conductive material to form an interconnect structure.
    Type: Application
    Filed: November 10, 2006
    Publication date: March 22, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Jin-Sheng Yang
  • Publication number: 20060240660
    Abstract: A semiconductor structure for a substrate having electronic elements formed thereon. The semiconductor structure comprises a dielectric layer and a conductive stuffing material. The dielectric layer is located over the substrate. It should be noticed that the dielectric layer has a plurality of trenched and a border shape of each trench is a non-straight shape. The conductive stuffing material fills the trenches to form an interconnect structure.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventor: Jin-Sheng Yang
  • Patent number: 6465360
    Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: October 15, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Jin-Sheng Yang, Tzung-Han Lee, Kun-Chi Lin
  • Publication number: 20020094693
    Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.
    Type: Application
    Filed: March 23, 2000
    Publication date: July 18, 2002
    Inventors: Jin-Sheng Yang, Tzung-Han Lee, Kun-Chi Lin
  • Patent number: 6361928
    Abstract: A method of defining a mask pattern for a photoresist layer in semiconductor fabrication. The method coats a photoresist layer containing an additive on a dielectric layer. The photoresist layer has an opening formed therein. The additive is 2,2′-azo-bis-isobutyronitride (AIBN) or phenyl-azo-triphenylmethane. The photoresist layer is exposed and developed. Then, a hard baking step is performed. A UV curing or a hot curing step is performed on the photoresist layer. As a result, the additive in the photoresist layer reacts to form nitrogen (N2) gas. Nitrogen gas makes the photoresist layer expand. The opening is decreased by the expansion of the photoresist layer. The dielectric layer is etched according to the expanded photoresist layer so that a via or a trench, which is smaller than a conventional one, is formed.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: March 26, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Jin-Sheng Yang, Tzung-Han Lee