Abstract: A refresh control circuit and semiconductor devices that may include an address counter for generating a counting address, a repetition address selector for generating a repetition address, a repetition refresh controller for generating a refresh repetition signal based on the counting address and repetition address, and a row decoder for selecting a row of a memory bank based on the counting address and the refresh repetition signal. A method for performing a refresh operation on a semiconductor device that may include receiving a refresh trigger, generating a counting address, generating a repetition address corresponding to a row having a degraded memory cell, providing a refresh repetition signal based on a comparison of the counting address and repetition address, and selecting a row to be refreshed based on one or more of the counting address, repetition address, and the refresh repetition address.