Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

Abstract: A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

Abstract: According to one embodiment of the present disclosure, there is provided a DC-DC converter including a slope compensation circuit configured to generate a sawtooth-shaped compensation ramp wave to output a slope voltage, a current sensing circuit configured to receive and convert a sensing current to output the converted current, and an adder configured to receive the slope voltage and the sensing current, wherein the adder includes a sensing resistor and a sensing switch, one end of the sensing resistor is connected to the current sensing circuit and the other end of the sensing resistor is connected to the sensing switch and the slope compensation circuit, and one end of the sensing switch is connected to the sensing resistor and the slope compensation circuit and the other end of the sensing switch is connected to the ground.

Abstract: A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

Abstract: The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.