Abstract: A display device includes a light emitting diode electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor electrically connected to the light emitting diode and a gate electrode of the driving transistor; and a connection electrode that connects the gate electrode of the driving transistor and the third transistor, wherein at least a part of a contact portion where the connection electrode contacts the third transistor does not overlap the first scan line.

Abstract: A display device includes a light emitting diode electrically connected between a driving voltage line and a common voltage line; a driving transistor electrically connected between the driving voltage line and the light emitting diode; a second transistor electrically connected between a first electrode of the driving transistor electrically connected to the driving voltage line and a data line; a first scan line electrically connected to a gate electrode of the second transistor; a third transistor electrically connected between a second electrode of the driving transistor electrically connected to the light emitting diode and a gate electrode of the driving transistor; and a connection electrode that connects the gate electrode of the driving transistor and the third transistor, wherein at least a part of a contact portion where the connection electrode contacts the third transistor does not overlap the first scan line.

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage.

Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage.

Abstract: A discrete multi-tone (DMT) processor receives predetermined control signals from a digital signal processor (DSP) within an asymmetric digital subscriber line (ADSL) modem, modulates transmission data in response to the control signals, and demodulates reception data. The DMT processor includes a frame synchronization signal generator, a transmitter, and a receiver. The frame synchronization generator generates a transmission frame synchronization signal and a reception frame synchronization signal in response to a cyclic prefix contained in the transmission data or reception data and a reception synchronization shift signal applied from the DSP. The transmitter DMT modulates and gain-controls the transmission data input in response to the transmission frame synchronization signal The receiver gain-controls and DMT demodulates the reception data response to the reception frame synchronization.

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system.

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system.

Abstract: A discrete multi-tone (DMT) processor in an asymmetric digital subscriber line (ADSL) modem receives predetermined control signals from a digital signal processor (DSP) within an asymmetric digital subscriber line (ADSL) modem, modulates transmission data in response to the control signals, and demodulates reception data. The DMT processor includes a frame synchronization signal generator, a transmitter, and a receiver. The frame synchronization generator generates a transmission frame synchronization signal and a reception frame synchronization signal in response to a cyclic prefix contained in the transmission data or reception data and a reception synchronization shift signal applied from the DSP. The transmitter DMT modulates and gain-controls the transmission data input through a first input terminal in response to the transmission frame synchronization signal and outputs the modulated and gain-controlled result through a first output terminal.

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system.

Abstract: A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data is sequentially stored head to tail so that memory space is not wasted.