Abstract: A vehicle loads at least one of a plurality of upper units having space to store a person or an object on an under unit including a drive mechanism that rotates wheels in the vehicle. The vehicle includes an under unit including a drive mechanism that rotates wheels and the at least one of the plurality of upper units loaded on the under unit. The under unit includes a loading unit, on which the at least one of the plurality of upper units as described above can be loaded. Each of the plurality of upper units includes a joint that joins to a different upper unit that is adjacently loaded.

Abstract: A lighting system includes a plurality of lighting devices and a control device. The plurality of lighting devices are installed in a facility. The control device controls the plurality of lighting devices. The control device controls lighting light projected by at least one lighting device, belonging to the plurality of lighting devices, into colored lighting light, of which a color is different from a color white, to give, upon acquiring information about an event in question, a sign depending on the event in question.

Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Abstract: An operation processing apparatus includes: a processor; and a memory coupled to the processor and configured to store a program, the processor, according to the program, performs: acquiring first data and second data from the memory in which the first data and second data are stored, the first data including pieces of element data arranged in the form of a matrix, the second data having an arrangement form obtained by removing a specific number of pieces of element data from the pieces of element data; converting the first data based on the arrangement form of the second data; and executing a convolution operation on the converted first data using the second data as a filter.

Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Abstract: A processing device includes a cache memory to temporarily register data stored in the main memory and a registration circuit that, when registering the data stored in the main memory to the cache memory, acquires identification information set in association with an area in that the data to be registered is stored in the main memory, and registers, in the cache memory, the identification information together with the data to be registered. The processing device further includes a comparison circuit that, when executing an instruction to access the main memory, compares access information specified together with an address of an access destination and identification information registered together with access object data in the cache memory, with each other. The processing device yet further includes an access limitation circuit that stops execution of the instruction to access the main memory in accordance with a result of the comparison.

Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Abstract: A system to which the present application is applied includes a semiconductor apparatus including: a first communication unit which communicates with a central processing unit; a second communication unit which communicates with another data processing apparatus through a slot connectable to the central processing unit; and an interruption notification unit which notifies a management apparatus of an interruption from the central processing unit. As a result, when the semiconductor apparatus is applied to a system without a communication function for communicating with another data processing apparatus, the semiconductor apparatus enables the connection to the other data processing apparatus.

Abstract: When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus.

Abstract: According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.

Abstract: The method for reconfiguring an information processing apparatus includes: transmitting, by the system management unit, a register setting request to set a register included in the control unit to a predetermined value to all of the system boards within the information processing apparatus, when a system board is added to or removed from any of the partitions; setting, by the system board that receives the register setting request, a register of a control unit of the local system board to the predetermined value, if a partition to which the local system board belongs includes the system board to be added or removed; and ignoring, by the system board that receives the register setting request, the register setting request if the partition to which the local system board belongs does not include the system board to be added or removed.

Abstract: According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.

Abstract: A memory access system has a first memory for storing data, a second memory for storing data, a processor for processing data, the processor including a first memory controller for reading out data from or writing data into the first memory, a second memory controller connected to the processor, for reading out data from or writing data into the first memory and the second memory, and a selector for selecting either the first memory controller or the second memory controller, and enabling either the first and the second memory controllers to read out data from or write data into the first memory.

Abstract: The method for reconfiguring an information processing apparatus includes: transmitting, by the system management unit, a register setting request to set a register included in the control unit to a predetermined value to all of the system boards within the information processing apparatus, when a system board is added to or removed from any of the partitions; setting, by the system board that receives the register setting request, a register of a control unit of the local system board to the predetermined value, if a partition to which the local system board belongs includes the system board to be added or removed; and ignoring, by the system board that receives the register setting request, the register setting request if the partition to which the local system board belongs does not include the system board to be added or removed.

Abstract: An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.

Abstract: An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.

Abstract: A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.

Abstract: A system controller includes an address map storage unit that stores therein an address map that includes mapped areas for accessing FWH that are mounted inside the same data processor. An target determining unit compares, upon receiving an input output request from a CPU, an address included in the input output request with the address map, and transfers the input output request to other system controller mounted in the data processor if the address is included in an area corresponding to the FWH that is not locally connected to the system controller.

Abstract: The object of the present invention is to provide an optimizing method for a groove structure of a friction disk of a wet-type friction engaging element, which can reduce drag torque by increasing outgoing flow of lubricating oil on the friction surface and increasing the content of air in the lubricating oil.