Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A method of manufacturing a high voltage device is described. A well region is formed within a substrate of a high voltage device region. A gate structure is made up of a gate oxide layer, a gate and an optional cap layer that are sequentially formed upon the well. Subsequently, using the gate structure as a mask, a large tilt angle light doping process is performed on the well of the high voltage device region of the well, thereby forming a lightly doped source and drain region. Thereupon, a optional thermal drive-in procedure is performed. Next, a spacer is formed on the side of the gate structure. Using the spacer and the gate structure as a mask, a heavy doping self-aligned ion implantation process is performed on the active region of the well, thereby forming a heavily doped source and drain region.