Patents by Inventor Jin-Uk Luke Shin

Jin-Uk Luke Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Duplicate bitline self-time technique for reliable memory operation
    Patent number: 6212117
    Abstract: A CMOS memory array, including a number of bit cells arranged in an array of N rows and M columns includes a duplicate column of bit cells that is used for self-timing. Receipt of an address will access a predetermined number of the bit cells to generate a reset signal that is used to enable sense amplifiers for sampling bit lines of the array.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: April 3, 2001
    Assignee: Hitachi Ltd.
    Inventors: Jin-Uk Luke Shin, Kenichi Osada, Masood Khan
  • Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory
    Patent number: 6011719
    Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1.times. and 2.times. architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: January 4, 2000
    Assignee: Motorola, Inc.
    Inventors: Karl L. Wang, Jin-Uk "Luke" Shin
  • Pipelined fast-access floating gate memory architecture and method of operation
    Patent number: 5901086
    Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: May 4, 1999
    Assignee: Motorola, Inc.
    Inventors: Karl L. Wang, Jin-Uk "Luke" Shin