Patents by Inventor Jin-won Jun

Jin-won Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7361565
    Abstract: In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Ho Shin, Jong-Hyon Ahn, Kong-Soo Cheong, Jin-Won Jun
  • Publication number: 20050158935
    Abstract: In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 21, 2005
    Inventors: Jeong-Ho Shin, Jong-Hyon Ahn, Kong-Soo Cheong, Jin-Won Jun
  • Patent number: 6911397
    Abstract: A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: June 28, 2005
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jin-Won Jun, Young-Wug Kim, Tae-Soo Park, Kyung-Tae Lee
  • Patent number: 6878598
    Abstract: Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 12, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-won Jun, Kong-soo Cheong, Jeong-ho Shin
  • Publication number: 20040132274
    Abstract: Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.
    Type: Application
    Filed: December 9, 2003
    Publication date: July 8, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Won Jun, Kong-Soo Cheong, Jeong-Ho Shin
  • Publication number: 20030199169
    Abstract: A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 23, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Won Jun, Young-Wug Kim, Tae-soo Park, Kyung-Tae Lee