Patents by Inventor Jin-Woo Moon
Jin-Woo Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951999Abstract: Proposed is a method of managing an error of a control unit for a vehicle, the method including: collecting an error; converting the collected error into a database in a form required for a diagnosis and debugging; and performing a recovery mechanism by interworking a platform health management cluster (PHM), a statement management cluster (SM), and an execution management cluster (EM), in which the collecting of the error includes: collecting a user error occurring in an application for a vehicle; collecting a platform error occurring in at least one of the platform health management cluster (PHM), the statement management cluster (SM), and the execution management cluster (EM); or collecting an integrated error according to whether a network management cluster (NM), a time synchronization cluster (TS), and a persistency cluster (PER) are normally operated.Type: GrantFiled: November 4, 2021Date of Patent: April 9, 2024Assignee: HYUNDAI AUTOEVER CORP.Inventor: Jin Woo Moon
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Patent number: 11949881Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.Type: GrantFiled: April 1, 2021Date of Patent: April 2, 2024Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong UniversityInventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
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Patent number: 11948709Abstract: An all-printed physically unclonable function based on a single-walled carbon nanotube network. The network may be a mixture of semiconducting and metallic nanotubes randomly tangled with each other through the printing process. The unique distribution of carbon nanotubes in a network can be used for authentication, and this feature can be a secret key for a high level hardware security. The carbon nanotube network does not require any advanced purification process, alignment of nanotubes, high-resolution lithography and patterning. Rather, the intrinsic randomness of carbon nanotubes is leveraged to provide the unclonable aspect.Type: GrantFiled: February 8, 2022Date of Patent: April 2, 2024Assignee: Universities Space Research AssociationInventors: Jin-Woo Han, Meyya Meyyappan, Dong-Il Moon
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Publication number: 20220185301Abstract: Proposed is a method of managing an error of a control unit for a vehicle, the method including: collecting an error; converting the collected error into a database in a form required for a diagnosis and debugging; and performing a recovery mechanism by interworking a platform health management cluster (PHM), a statement management cluster (SM), and an execution management cluster (EM), in which the collecting of the error includes: collecting a user error occurring in an application for a vehicle; collecting a platform error occurring in at least one of the platform health management cluster (PHM), the statement management cluster (SM), and the execution management cluster (EM); or collecting an integrated error according to whether a network management cluster (NM), a time synchronization cluster (TS), and a persistency cluster (PER) are normally operated.Type: ApplicationFiled: November 4, 2021Publication date: June 16, 2022Inventor: Jin Woo MOON
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Patent number: 9741844Abstract: Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer.Type: GrantFiled: December 20, 2013Date of Patent: August 22, 2017Assignee: Magnachip Semiconductor, Ltd.Inventors: Young Bae Kim, Jin Woo Moon, Francois Hebert
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Patent number: 9257502Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.Type: GrantFiled: June 26, 2013Date of Patent: February 9, 2016Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Min-suk Kim, Sun-hak Lee, Jin-woo Moon, Hye-mi Kim
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Patent number: 9245997Abstract: A method of fabricating a semiconductor device capable of increasing a breakdown voltage without an additional epitaxial layer or buried layer with respect to a high-voltage horizontal MOSFET.Type: GrantFiled: August 6, 2014Date of Patent: January 26, 2016Assignee: Magnachip Semiconductor, Ltd.Inventors: Francois Hebert, I-Shan Sun, Young Bae Kim, Young Ju Kim, Kwang Il Kim, In Taek Oh, Jin Woo Moon
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Patent number: 9236470Abstract: A semiconductor power device and a method of fabricating the same are provided. The semiconductor power device involving: a first conductivity type semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a second conductivity type well formed in the semiconductor substrate and the epitaxial layer; a drain region formed in the well; an oxide layer that insulates a gate region from the drain region; a first conductivity type buried layer formed in the well; a second conductivity type drift region surrounding the buried layer; and a second conductivity type TOP region formed between the buried layer and the oxide layer.Type: GrantFiled: December 23, 2013Date of Patent: January 12, 2016Assignee: MagnaChip Semiconductor, Ltd.Inventors: Francois Hebert, Young Bae Kim, Jin Woo Moon, Kyung Ho Lee
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Publication number: 20150041894Abstract: A method of fabricating a semiconductor device capable of increasing a breakdown voltage without an additional epitaxial layer or buried layer with respect to a high-voltage horizontal MOSFET.Type: ApplicationFiled: August 6, 2014Publication date: February 12, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Francois Hebert, I-Shan Sun, Young Bae Kim, Young Ju Kim, Kwang Il Kim, In Taek Oh, Jin Woo Moon
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Publication number: 20140353749Abstract: A semiconductor power device and a method of fabricating the same are provided. The semiconductor power device involving: a first conductivity type semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a second conductivity type well formed in the semiconductor substrate and the epitaxial layer; a drain region formed in the well; an oxide layer that insulates a gate region from the drain region; a first conductivity type buried layer formed in the well; a second conductivity type drift region surrounding the buried layer; and a second conductivity type TOP region formed between the buried layer and the oxide layer.Type: ApplicationFiled: December 23, 2013Publication date: December 4, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Francois HEBERT, Young Bae KIM, Jin Woo MOON, Kyung Ho LEE
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Publication number: 20140306285Abstract: Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer.Type: ApplicationFiled: December 20, 2013Publication date: October 16, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Young Bae KIM, Jin Woo MOON, Francois HEBERT
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Publication number: 20130341718Abstract: In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.Type: ApplicationFiled: June 26, 2013Publication date: December 26, 2013Inventors: Min-suk KIM, Sun-hak LEE, Jin-woo MOON, Hye-mi KIM
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Patent number: 7960952Abstract: A switching mode power supply and a switch thereof are provided. The switch includes a plurality of first transistors, and a second transistor that is turned on/off by a control signal that is equal to that of the plurality of first transistors and in which a second current corresponding to a first current flowing to the plurality of first transistors flows, wherein a ratio of the first current to the second current sequentially changes from a time point at which the second transistor is turned on. Therefore, a switching mode power supply and a switch thereof that can always uniformly sustain a maximum limit current flowing to the switch regardless of a level of an input voltage without including a special additional circuit can be provided.Type: GrantFiled: April 18, 2008Date of Patent: June 14, 2011Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Gwan-Bon Koo, Jin-Tae Kim, Yoo-Woong Hwang, Kyung Oun Jang, Jin-Woo Moon, Sang-Hyun Lee
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Publication number: 20080258564Abstract: A switching mode power supply and a switch thereof are provided. The switch includes a plurality of first transistors, and a second transistor that is turned on/off by a control signal that is equal to that of the plurality of first transistors and in which a second current corresponding to a first current flowing to the plurality of first transistors flows, wherein a ratio of the first current to the second current sequentially changes from a time point at which the second transistor is turned on. Therefore, a switching mode power supply and a switch thereof that can always uniformly sustain a maximum limit current flowing to the switch regardless of a level of an input voltage without including a special additional circuit can be provided.Type: ApplicationFiled: April 18, 2008Publication date: October 23, 2008Inventors: Gwan-Bon Koo, Jin-Tae Kim, Yoo-Woong Hwang, Kyung-Oun Jang, Jin-Woo Moon, Sang-Hyun Lee