Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode disposed alternately with the dielectric layer; and an external electrode disposed on the body, wherein the dielectric layer includes a first region extending from an interfacial surface with the internal electrode to 50 nm of the dielectric layer in an inward direction and a second region excluding the first region, and wherein, in the first region, an average content of In based on overall elements excluding oxygen is 0.5 at % or more and 2.0 at % or less, and an average content of Sn based on overall elements excluding oxygen is 0.5 at % or more and 1.75 at % or less.

Abstract: An RF cavity filter is disclosed. The disclosed filter includes: a housing in which there is at least one cavity formed; a cover joined to an upper portion of the housing; at least one bolt inserted through at least one through hole formed in the cover; and at least one elastic element attached to the cover in an area below the through hole, where the bolt is inserted through the through hole to provide an external force on the elastic element, and the external force alters the shape of the elastic element. With the disclosed filter, pieces of metal debris created during tuning can be prevented from reaching the inside of the filter, and the degradation in the PIMD performance that would have otherwise occurred due to the pieces of debris can be avoided. Also, the filter can maintain a tuned state without the use of separate nuts.

Abstract: An RF cavity filter is disclosed. The disclosed filter includes: a housing in which there is at least one cavity formed; a cover joined to an upper portion of the housing; at least one bolt inserted through at least one through hole formed in the cover; and at least one elastic element attached to the cover in an area below the through hole, where the bolt is inserted through the through hole to provide an external force on the elastic element, and the external force alters the shape of the elastic element. With the disclosed filter, pieces of metal debris created during tuning can be prevented from reaching the inside of the filter, and the degradation in the PIMD performance that would have otherwise occurred due to the pieces of debris can be avoided. Also, the filter can maintain a tuned state without the use of separate nuts.

Abstract: A frequency tunable filter comprises a housing having a plurality of walls therein defining a plurality of cavities; a cover mounted on the housing; a plurality of resonators contained in the cavities; at least one sliding member located between the cover and the resonators; and a plurality of metal tuning elements attached to a lower part of the sliding member, wherein frequency tuning is performed by sliding of the sliding member.

Abstract: A frequency tunable filter comprises a housing having a plurality of walls therein defining a plurality of cavities; a cover mounted on the housing; a plurality of resonators contained in the cavities; at least one sliding member located between the cover and the resonators; and a plurality of metal tuning elements attached to a lower part of the sliding member, wherein frequency tuning is performed by sliding of the sliding member.

Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.

Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.