Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: Disclosed is a miniaturized battery module in which a space except for a space of a battery cell is minimized and the number of components is reduced. The miniaturized battery module includes a cell assembly configured by assembling a plurality of battery cells, an upper frame inserted into an outer upper surface of the cell assembly, a lower frame inserted into an outer lower surface of the cell assembly and fastened to the upper frame, and first and second endplates fastened to two opposite ends of the cell assembly and configured to fix the plurality of battery cells. In this case, at least two or more of the plurality of the battery cells are arranged side by side, and the upper frame and the lower frame are fastened by welding.

Abstract: A display device includes a sensing circuit and a controller which selects a pixel row in a frame period. A vertical blank period of the frame period includes a sensing time in which the sensing circuit performs a sensing operation for the selected pixel row. The sensing circuit measures a first source voltage of a driving transistor of a pixel in the selected pixel row at a first time point of the sensing time, and measures a second source voltage of the driving transistor at a second time point of the sensing time. The controller calculates a threshold voltage parameter and a mobility parameter based on the first and second source voltages, predicts a saturated source voltage of the driving transistor based on the threshold voltage parameter and the mobility parameter, and calculates a threshold voltage of the driving transistor based on the saturated source voltage.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.

Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells; a top plate configured to cover an upper side of the battery cell assembly; a bottom plate configured to cover a lower side of the battery cell assembly; a sensing assembly disposed to cover a front side and a rear side of the battery cell assembly; a pair of side plates disposed at side surfaces, respectively, of the battery cell assembly; and a pair of compression pads disposed between the pair of side plates and the battery cell assembly, respectively.

Abstract: Disclosed is a method of decoding an image and a method of encoding an image. The method of decoding an image includes: obtaining motion-constrained tile set information; determining, on the basis of the motion-constrained tile set information, a first boundary region of a collocated tile set within a reference picture, which corresponds to a motion-constrained tile set; padding a second boundary region corresponding to the first boundary region; and performing inter prediction on the motion-constrained tile set by using a collocated tile set that includes the padded second boundary region.

Abstract: An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.