Patents by Inventor Jin-Yeong Son
Jin-Yeong Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11171222Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.Type: GrantFiled: May 31, 2019Date of Patent: November 9, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan Kim, Jin Yeong Son
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Patent number: 11133414Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.Type: GrantFiled: April 17, 2020Date of Patent: September 28, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
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Patent number: 10777551Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: GrantFiled: December 16, 2019Date of Patent: September 15, 2020Assignee: Magnachip Semiconductor, Ltd.Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
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Publication number: 20200251575Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.Type: ApplicationFiled: May 31, 2019Publication date: August 6, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Guk Hwan KIM, Jin Yeong SON
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Publication number: 20200251592Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.Type: ApplicationFiled: April 17, 2020Publication date: August 6, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Jae Hyung JANG, Jin Yeong SON, Hee Hwan JI
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Patent number: 10727300Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.Type: GrantFiled: January 12, 2018Date of Patent: July 28, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan Kim, Jin Yeong Son
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Patent number: 10700198Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.Type: GrantFiled: March 28, 2018Date of Patent: June 30, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
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Patent number: 10686071Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.Type: GrantFiled: September 12, 2018Date of Patent: June 16, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
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Publication number: 20200118998Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: Magnachip Semiconductor, Ltd.Inventors: Young Bae KIM, Kwang II KIM, Jun Hyun KIM, In Sik JUNG, Jae Hyung JANG, Jin Yeong SON
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Patent number: 10573645Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: GrantFiled: September 25, 2018Date of Patent: February 25, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
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Patent number: 10381460Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: GrantFiled: January 27, 2017Date of Patent: August 13, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Yu Shin Ryu, Bo Seok Oh, Jin Yeong Son
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Publication number: 20190043986Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.Type: ApplicationFiled: March 28, 2018Publication date: February 7, 2019Applicant: Magnachip Semiconductor, Ltd.Inventors: Jae Hyung JANG, Jin Yeong SON, Hee Hwan JI
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Publication number: 20190035783Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: ApplicationFiled: September 25, 2018Publication date: January 31, 2019Applicant: Magnachip Semiconductor, Ltd.Inventors: Young Bae KIM, Kwang Il KIM, Jun Hyun KIM, In Sik JUNG, Jae Hyung JANG, Jin Yeong SON
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Publication number: 20190027600Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.Type: ApplicationFiled: September 12, 2018Publication date: January 24, 2019Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
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Publication number: 20190019866Abstract: A semiconductor device, includes a first conductive type first doping area, a second conductive type second doping area, a source region, a drain region, a gate insulating film, and a gate electrode. The first conductive type first doping area is formed in a substrate region. The second conductive type second doping area is formed in the substrate to be spaced apart from the first conductive type first doping area. The source region is formed in the first conductive type first doping area. The drain region is formed in the second conductive type second doping area. The gate insulating film is formed between the source region and the drain region. A thickness of a first end of the gate insulating film is different than a thickness of a second end of the gate insulating film. The gate electrode formed on the gate insulating film.Type: ApplicationFiled: January 12, 2018Publication date: January 17, 2019Applicant: MagnaChip Semiconductor, Ltd.Inventors: Guk Hwan KIM, Jin Yeong SON
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Patent number: 10115720Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: GrantFiled: January 30, 2017Date of Patent: October 30, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
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Patent number: 10103260Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.Type: GrantFiled: November 30, 2017Date of Patent: October 16, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
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Publication number: 20180286981Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain regionType: ApplicationFiled: November 30, 2017Publication date: October 4, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae Hyung JANG, Hee Hwan JI, Jin Yeong SON
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Publication number: 20170301668Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.Type: ApplicationFiled: January 30, 2017Publication date: October 19, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Young Bae KIM, Kwang Il KIM, Jun Hyun KIM, In Sik JUNG, Jae Hyung JANG, Jin Yeong SON
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Publication number: 20170141213Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Applicant: MagnaChip Semiconductor, Ltd.Inventors: Yu Shin RYU, Bo Seok OH, Jin Yeong SON