Patents by Inventor Jin Ying
Jin Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088327Abstract: A light emitting device includes a light-emitting laminate and an insulating reflective structure. The insulating reflective structure includes n pairs of dielectric layers stacked on the light-emitting laminate. Each of the n pairs of dielectric layers includes a first material layer and a second material layer. The first material layer has a first refractive index, and the second material layer has a second refractive index that is greater than the first refractive index of the first material layer. For each pair of dielectric layers among m1 pairs of dielectric layers out of the n pairs of dielectric layers, the first material layer has an optical thickness that is greater than that of the second material layer, where 0.5n?m1?n, and n and m1 are natural numbers greater than 0.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Shiwei LIU, Jin XU, Baojun SHI, Shuijie WANG, Ke LIU, Chung-ying CHANG
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Patent number: 9893625Abstract: Disclosed herein is a DC/DC power supply apparatus, which includes a plurality of power boards, a control board and a main board. The plurality of power boards are coupled in parallel with one another, and each power board includes a carrier circuit board and a power device disposed on the carrier circuit board. The control board includes a feedback control circuit and a PWM generator circuit; the feedback control circuit is configured to receive one or more feedback signals from the power boards; the PWM generator circuit outputs a PWM control signal to the power boards based on the feedback signal. The main board is electrically coupled to the power boards and the control board.Type: GrantFiled: March 19, 2015Date of Patent: February 13, 2018Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.Inventors: Wen-Hua Li, Sheng-Li Lu, Zhong-Wang Yang, Jin-Ying Zhang, Qiong Zhang
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Publication number: 20150303814Abstract: Disclosed herein is a DC/DC power supply apparatus, which includes a plurality of power boards, a control board and a main board. The plurality of power boards are coupled in parallel with one another, and each power board includes a carrier circuit board and a power device disposed on the carrier circuit board. The control board includes a feedback control circuit and a PWM generator circuit; the feedback control circuit is configured to receive one or more feedback signals from the power boards; the PWM generator circuit outputs a PWM control signal to the power boards based on the feedback signal. The main board is electrically coupled to the power boards and the control board.Type: ApplicationFiled: March 19, 2015Publication date: October 22, 2015Inventors: Wen-Hua Li, Sheng-Li Lu, Zhong-Wang Yang, Jin-Ying Zhang, Qiong Zhang
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Patent number: 8836038Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: GrantFiled: September 16, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee
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Patent number: 8384159Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: GrantFiled: April 20, 2009Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Patent number: 7939396Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.Type: GrantFiled: June 9, 2006Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Publication number: 20110001194Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, K. T. Huang, Tze-Liang Lee
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Patent number: 7824990Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.Type: GrantFiled: January 10, 2006Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Vincent S. Chang, Fong-Yu Yen, Peng-Soon Lim, Jin Ying, Hun-Jan Tao
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Patent number: 7812414Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: GrantFiled: January 23, 2007Date of Patent: October 12, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee
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Patent number: 7732878Abstract: A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.Type: GrantFiled: October 18, 2006Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Gi Yao, Shiang-Bau Wang, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Publication number: 20090315125Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: ApplicationFiled: April 20, 2009Publication date: December 24, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yu YEN, Cheng-Lung HUNG, Peng-Fu HSU, Vencent S. CHANG, Yong-Tian HOU, Jin YING, Hun-Jan TAO
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Patent number: 7531399Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.Type: GrantFiled: September 15, 2006Date of Patent: May 12, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Patent number: 7465634Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.Type: GrantFiled: October 18, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080173947Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: ApplicationFiled: January 23, 2007Publication date: July 24, 2008Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, K. T. Huang, Tze-Liang Lee
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Publication number: 20080096336Abstract: An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Peng-Soon Lim, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080093675Abstract: A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Liang-Gi Yao, Shiang-Bau Wang, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Publication number: 20080093682Abstract: Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Liang-Gi Yao, Jin Ying, Hun-Jan Tao, Shih-Chang Chen, Mong-Song Liang
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Publication number: 20080070395Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080050879Abstract: A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby defining a gate structure.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Lung Hung, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Publication number: 20080001237Abstract: Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Vincent S. Chang, Peng-Fu Hsu, Fong-Yu Yen, Yong-Tian Hou, Jin Ying, Hun-Jan Tao