Abstract: An image sensor includes: a substrate including a first surface and a second surface on which light is incident, the second surface being opposite to the first surface; a photoelectric converter provided in the substrate; a first metal layer provided on the first surface of the substrate; a second metal layer provided on the first metal layer; and a capacitor layer provided between the first metal layer and the second metal layer, wherein the capacitor layer includes: a first lower electrode electrically connected to the first metal layer, a first upper electrode electrically connected to the second metal layer, a second upper electrode spaced apart from the first upper electrode and electrically connected to the second metal layer, a first capacitor provided between the first lower electrode and the first upper electrode, and a second capacitor provided between the first lower electrode and the second upper electrode.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: A memory controller and a storage device including the same are provided. The memory controller for performing a buffering operation of temporarily storing data to be written to a non-volatile memory and data to be read from the non-volatile memory in a buffer memory includes a buffer request queue configured to store a plurality of buffer write requests requesting data to be temporarily stored in the buffer memory and a plurality of buffer read requests requesting data stored in the buffer memory to be read, a buffer traffic monitor configured to calculate the total amount of requested data in real time by summing the lengths of data specified in the respective buffer write requests and the respective buffer read requests stored in the buffer request queue, and a buffer manager configured to control execution of the buffering operation by setting an execution ratio based on the total amount of requested data calculated in real time.

Abstract: An image sensor includes: a substrate including a first surface and a second surface on which light is incident, the second surface being opposite to the first surface; a photoelectric converter provided in the substrate; a first metal layer provided on the first surface of the substrate; a second metal layer provided on the first metal layer; and a capacitor layer provided between the first metal layer and the second metal layer, wherein the capacitor layer includes: a first lower electrode electrically connected to the first metal layer, a first upper electrode electrically connected to the second metal layer, a second upper electrode spaced apart from the first upper electrode and electrically connected to the second metal layer, a first capacitor provided between the first lower electrode and the first upper electrode, and a second capacitor provided between the first lower electrode and the second upper electrode.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: A memory controller and a storage device including the same are provided. The memory controller for performing a buffering operation of temporarily storing data to be written to a non-volatile memory and data to be read from the non-volatile memory in a buffer memory includes a buffer request queue configured to store a plurality of buffer write requests requesting data to be temporarily stored in the buffer memory and a plurality of buffer read requests requesting data stored in the buffer memory to be read, a buffer traffic monitor configured to calculate the total amount of requested data in real time by summing the lengths of data specified in the respective buffer write requests and the respective buffer read requests stored in the buffer request queue, and a buffer manager configured to control execution of the buffering operation by setting an execution ratio based on the total amount of requested data calculated in real time.

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: Image sensors are provided. The image sensor may include a substrate including a first surface and a second surface opposite the first surface, a photoelectric conversion layer in the substrate, and a lower capacitor connection pattern on the first surface of the substrate. The second surface of the substrate may be configured to receive incident light. The lower capacitor connection pattern may include a capacitor region and a landing region protruding from the capacitor region. The image sensors may also include a capacitor structure including a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the capacitor region, a first wire on the capacitor structure and connected to the second conductive pattern, and a second wire connected to the landing region. The first conductive pattern may be connected to the lower capacitor connection pattern.

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.

Abstract: A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

Abstract: A Flash Translation Layer (FTL) structure including mapping information for storing data is disclosed. The FTL structure includes a plurality of hierarchical data groups including a zeroth-layer host data group, and first-layer to nth-layer metadata groups, and zeroth to nth logs configured in a hierarchical structure in correspondence with the respective hierarchical data groups, for processing data of the corresponding data groups. A kth log (0?k?n) provides an interface to volatile memory resources dividedly allocated to the kth log, an interface to non-volatile memory resources dividedly allocated to the kth log, and an interface to at least one of (k?1)th and (k+1)th logs.

Abstract: The present invention provides a thermoelectric generator module including a set of module unit bodies disposed between a hot source and a cold source to serve as fundamental structures for performing thermoelectric power generation and a method of manufacturing the thermoelectric generator module. Each of the module unit bodies comprises: a first electrodes disposed at one of the hot source and the cold source; a second electrode disposed at the other of the hot source and the cold source so as to be spaced apart from the first electrodes; a first nanowire configured to interconnect the first electrode and the second electrode and composed of an n-type or p-type semiconductor; and a second nanowire.

Abstract: A Flash Translation Layer (FTL) structure including mapping information for storing data is disclosed. The FTL structure includes a plurality of hierarchical data groups including a zeroth-layer host data group, and first-layer to nth-layer metadata groups, and zeroth to nth logs configured in a hierarchical structure in correspondence with the respective hierarchical data groups, for processing data of the corresponding data groups. A kth log (0?k?n) provides an interface to volatile memory resources dividedly allocated to the kth log, an interface to non-volatile memory resources dividedly allocated to the kth log, and an interface to at least one of (k?1)th and (k+1)th logs.

Abstract: The present invention provides a method of manufacturing a nanofiber-based thermoelectric generator module, the method comprising: an electrode formation step of forming a plurality of electrodes and a plurality of second electrodes so as to be spaced apart from and opposite to each other in an alternately staggered arrangement relative to each other; a first nanofiber arrangement step of arranging a first nonofiber including an n-type or p-type semiconductor; and a second nanofiber arrangement step of arranging a second nonofiber including a semiconductor of a type different from the type of the semiconductor forming the first nanofiber, a nanofiber-based thermoelectric generator module manufactured by the method, and an electrospinning apparatus of manufacturing nanofibers for the nanofiber-based thermoelectric generator module.