Abstract: Disclosed is a method of processing item sales information by an electronic apparatus including acquiring a purchase request including item information related to an item selected by a user and information related to a payment means, providing a purchase response including approval information corresponding to the purchase request before proceeding with payment through the payment means in response to the purchase request when the information related to the payment means satisfies a first condition, transmitting a release request for the item to a first server; and requesting payment for at least some of an amount corresponding to one or more purchase requests related to the payment means according to an arrival of settlement timing corresponding to the payment means.

Abstract: An address decoder and a semiconductor memory device including the same are disclosed, which relate to a technology for a decoding circuit configured to decode a column address. The address decoder includes a pre-decoder and a column decoder. The pre-decoder divides a plurality of pre-decoding signals into at least one column address group by decoding column addresses, outputs the pre-decoding signals for each group, and outputs a second pre-decoding signal group which is an inverted signal of a first pre-decoding signal group from among the plurality of pre-decoding signals. The column decoder outputs column selection signals by decoding the plurality of pre-decoding signals in a manner that operation of a metal oxide semiconductor (MOS) transistor is controlled by the first pre-decoding signal group and the second pre-decoding signal group.

Abstract: An address decoder and a semiconductor memory device including the same are disclosed, which relate to a technology for a decoding circuit configured to decode a column address. The address decoder includes a pre-decoder and a column decoder. The pre-decoder divides a plurality of pre-decoding signals into at least one column address group by decoding column addresses, outputs the pre-decoding signals for each group, and outputs a second pre-decoding signal group which is an inverted signal of a first pre-decoding signal group from among the plurality of pre-decoding signals. The column decoder outputs column selection signals by decoding the plurality of pre-decoding signals in a manner that operation of a metal oxide semiconductor (MOS) transistor is controlled by the first pre-decoding signal group and the second pre-decoding signal group.

Abstract: A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. The bank address controller generates a write address and a read address designating an address for the precharge operation in response to a write bank address and a read bank address. The precharge signal generator generates a precharge signal for performing the precharge operation in a bank selected in response to the write address when the write precharge signal is activated, or generates a precharge signal for performing the precharge operation in a bank selected in response to the read address when the read precharge signal is activated.

Abstract: A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. The bank address controller generates a write address and a read address designating an address for the precharge operation in response to a write bank address and a read bank address. The precharge signal generator generates a precharge signal for performing the precharge operation in a bank selected in response to the write address when the write precharge signal is activated, or generates a precharge signal for performing the precharge operation in a bank selected in response to the read address when the read precharge signal is activated.