Patents by Inventor Jin Yuan

Jin Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12368438
    Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
    Type: Grant
    Filed: November 4, 2023
    Date of Patent: July 22, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 12354966
    Abstract: A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: July 8, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250212423
    Abstract: A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling
    Type: Application
    Filed: March 16, 2025
    Publication date: June 26, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250191993
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate, a first semiconductor die disposed on the substrate, and a second semiconductor die disposed on the substrate spaced from the first semiconductor die to define a gap between the first semiconductor die and the second semiconductor die. The semiconductor device assembly may include a thermally-conductive filler disposed in the gap between the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 12, 2025
    Inventors: Chesheng KUNG, Chien Hao HSU, Hung Wen LIU, Vladimir NOVESKI, Jin Yuan LAI
  • Patent number: 12327790
    Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur
    Type: Grant
    Filed: January 7, 2024
    Date of Patent: June 10, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 12327813
    Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equa
    Type: Grant
    Filed: March 9, 2024
    Date of Patent: June 10, 2025
    Assignee: iCometrue Company
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 12327816
    Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: June 10, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250149504
    Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space
    Type: Application
    Filed: January 12, 2025
    Publication date: May 8, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250149529
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Application
    Filed: January 12, 2025
    Publication date: May 8, 2025
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20250149505
    Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space
    Type: Application
    Filed: January 12, 2025
    Publication date: May 8, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250125241
    Abstract: A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having a top surface, a bottom surface opposite to the top surface of the second substrate and a side surface joining an edge of the top surface of the second substrate and joining an edge of the bottom surface of the second substrate, wherein the side surface of the second substrate faces the side surface of the first substrate, wherein the top surfaces of the first and second substrates are coplanar with each other at a top of the connector and the bottom surfaces of the first and second substrates are coplanar with each other at a bottom of the connector; and a plurality of metal traces between, in a first horizontal direction, the side surfaces of the first and second substrates, wherein each of the plurality of metal
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Ping-Jung Yang, Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Chiu-Ming Chou
  • Publication number: 20250125273
    Abstract: A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-array (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ba
    Type: Application
    Filed: December 1, 2024
    Publication date: April 17, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 12278192
    Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s
    Type: Grant
    Filed: October 1, 2023
    Date of Patent: April 15, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250118721
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; afield-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Application
    Filed: December 15, 2024
    Publication date: April 10, 2025
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 12268012
    Abstract: A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: April 1, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250105238
    Abstract: A multi-chip package includes a first IC chip; a first sealing layer at a same first horizontal level as the first IC chip; a first silicon-oxide-containing layer over the first IC chip and first sealing layer and across an edge of the first IC chip; a first bonding pad in a first opening in the first silicon-oxide-containing layer, wherein the first bonding pad has a copper layer in the first opening; a second IC chip over the first IC chip; a second sealing layer at a same second horizontal level as the second IC chip; a second silicon-oxide-containing layer under the second IC chip and having a bottom surface bonded to and in contact with a top surface of the first silicon-oxide-containing layer; a second bonding pad under the second IC chip, in a second opening in the second silicon-oxide-containing layer and coupling to the second IC chip, wherein the second bonding pad has a copper layer in the second opening and having a bottom surface bonded to and in contact with a top surface of the copper layer of
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ping-Jung Yang
  • Publication number: 20250096131
    Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top sur
    Type: Application
    Filed: October 20, 2024
    Publication date: March 20, 2025
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 12255195
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 18, 2025
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Publication number: 20250077754
    Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20250081600
    Abstract: A semiconductor integrated-circuit (IC) chip includes: a first transistor, a second transistor at a same horizontal level as the first transistor, a first oxide layer at the same horizontal level as the first and second transistors, horizontally around the first and second transistors and having a portion horizontally between the first and second transistors; a frontside interconnection scheme under the first and second transistors and first oxide layer, a backside interconnection scheme over the first and second transistor and first oxide layer, and a metal interconnect vertically in the portion of the first oxide layer and coupling the frontside interconnection scheme to the backside interconnection scheme.
    Type: Application
    Filed: September 4, 2024
    Publication date: March 6, 2025
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin