Abstract: The present disclosure relates to a novel citrate synthase variant, a microorganism comprising the variant, and a method for producing O-acetyl-L-homoserine and L-methionine using the microorganism.

Abstract: Provided are a method for preparing a pixel defining layer comprising applying and coating, pre-baking, exposing to light, developing, and post-baking of a photosensitive composition containing a colorant having a pigment with an average particle size of 100 nm or less, wherein the coated film generated after the post-baking has an optical density of 0.8/?m to 2.0/?m, a roughness of 3.0 nm or less, and no residue; and an organic light emitting display device comprising the pixel defining layer obtained by the method which has improved display reliability and lifetime as well as vivid colors.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.

Abstract: There is provided an additive for secondary battery electrolyte, containing aluminum silicate. The aluminum silicate has a particle size of 200 nm to 20 ?m. The aluminum silicate has a mass ratio of 60 to 70 wt % of oxygen (O), 0.1 to 2.0 wt % of aluminum (Al), and 25 to 35 wt % of silicon (Si). The aluminum silicate has a surface area of 50 to 1,000 m2/g. The aluminum silicate has a pore size of 0.1 to 20 nm.

Abstract: There is provided an additive, containing magnesium silicate, for a secondary battery electrolyte and a preparation method therefor. The magnesium silicate has a mass ratio of 50 to 70 wt % of oxygen (O), 5 to 20 wt % of magnesium (Al), and 15 to 35 wt % of silicon (Si). The magnesium silicate has a surface area of 50 to 500 m2/g. The magnesium silicate has a pore size of 0.1 to 20 nm.

Abstract: An object of the present disclosure is to improve display reliability and lifetime as well as vivid colors. When there remain residues in the washing part due to incomplete removal during the developing step, it can cause dark spots or pixel off due to the residues, and thus residue-free pixels can be formed by optimizing the temperature and time for developing. Additionally, when the amount of outgas in the panel after post-baking is 15 ppm or more, it may cause a reduction in luminance and lifetime due to pixel shrinkage. Therefore, in order to minimize the amount of outgas after completion of the post-baking process, the generation of outgas in the panel state can be minimized by generating sufficient fume in the post-baking step, in addition to forming clean pixels in the developing step.

Abstract: A Merkle tree-based data management method may comprise: aligning data into two-dimensional square matrix; calculating a hash value of each node of the two-dimensional square matrix; calculating hash values of each row of the two-dimensional square matrix; generating an additional column with nodes having the hash values of each row; calculating hash values of each column of the two-dimensional square matrix; generating an additional row with nodes having hash values of each column; and calculating a Merkle root by concatenating the hash values of the additional column and the hash values of the additional row.

Abstract: A display device includes a first electrode and a second electrode extending in one direction on a substrate and spaced from each other, a first insulating layer on the first electrode and the second electrode, and a plurality of light emitting elements located on the first electrode and the second electrode, the plurality of light emitting elements being on the first insulating layer, wherein each of the first electrode and the second electrode includes a main electrode portion and a plurality of sub-electrode portions having a thickness smaller than that of the main electrode portion, the plurality of sub-electrode portions of each of the first electrode and the second electrode are connected to respective sides of the main electrode portion of the corresponding ones of the first electrode and the second electrode in the one direction.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A liquid crystal display apparatus includes a first substrate on which a pixel area is defined, a second substrate facing the first substrate, and liquid crystals interposed between the first and second substrates. The pixel area is divided into a plurality of domains according to the alignment direction of the liquid crystals. The domains compensate for optical characteristics, thereby widening the viewing angle of the liquid crystal display apparatus. The liquid crystals include smectic liquid crystals that form a layered structure in a specific direction. When the liquid crystal display apparatus is driven, the smectic liquid crystals rapidly respond to the electric field, thereby improving the operational speed of the liquid crystal apparatus.

Abstract: A liquid crystal display is provided, which includes a first insulating substrate; a gate line formed on the first insulating substrate; a gate insulating layer formed on the gate line; a data line formed on the gate insulating layer, a passivation layer formed on the data line; a pixel electrode formed on the passivation layer and a first cutout pattern; a second insulating substrate facing the first insulating substrate; and a common electrode formed on the second insulating substrate and having a second cutout pattern, wherein width of the domains is equal to or less than 30 microns

Abstract: A liquid crystal display is provided, which includes a first insulating substrate; a pixel electrode formed on the first substrate and having a first aperture pattern; a thin film transistor formed on the first substrate and switching voltages applied to the pixel electrode; a second insulating substrate opposite to the first substrate; a reference electrode formed on the second substrate and having a second aperture pattern to partition the pixel electrode into a plurality of subareas together with the first aperture pattern; and a liquid crystal layer interposed between the first substrate and the second substrate and having the thickness ranging 3.4-4.0 ?m. The above described adjustment of the cell gap and the applied electric field can keep the response time of an LCD to be equal to or lower than a predetermined value.