Abstract: A multithread processor according to the inventive architecture is a clocked multithread processor for data processing of threads having a standard processor root unit (1) in which threads can be switched to a different thread T1 by means a thread switching trigger data field (11), triggered by the thread Tj which is currently to be processed by the standard processor root unit (1), without any clock cycle loss, with each program instruction Ijk for a thread Tj having a thread switching trigger data field (11) such as this.

Abstract: A method for compressing a data packet is proposed, the data packet comprising at least a first data block and a second data block, the first data block referring to the second data block. In the method, the second data block is compressed and it is noted in the data packet that the second data block has been compressed. In one embodiment, the method is suitable for IPv6 data packets, the second data block then being, for example, a routing header.

Abstract: Multichannel processor for processing data of multi-protocol data packets, comprising (a) a number of input ports (2) for receiving received data packets in parallel, which can be selected in each case by means of an input port number; (b) at least one multiplexer (3) connected to the input ports (2), which switches through the data present at the selected input port word by word; (c) at least one first programmable data processing unit (4), which separates the sequence of data words switched through by the multiplexer (3) into data packet header words and into data packet payload words in accordance with a sorting program selected in accordance with the input port number; (d) a buffer management unit (44) which writes the data packet payload words of a received data packet into an addressable payload memory (47) and generates localization data which specify the corresponding memory area; (e) a descriptor generator unit (43) for generating data packet descriptors which in each case contain a header assembled

Abstract: The invention relates to a method for calculating a least mean square algorithm using an N-tap filter. A modified least mean square algorithm is used for the calculation. In a first calculation step, calculation is effected using a first, wide bit width in the N taps. In a second step, depending on the result of the first calculation step, a second, smaller number of bits is selected for the further method steps.

Abstract: The invention relates to a data processing device for recovering digital data which is received in an analogue transmitted signal. According to the invention, the received signal is digitized and a threshold is determined in a threshold estimator. The interference in the channel is corrected in a downstream adaptive equalizer, and a bit clock generator produces the correct sampling rate and phase for the data of a line. The threshold estimator is used to determine the mean value of an input signal for each line, and this value is then taken as the optimum decision value for sampling the data bits for this line. By using an adaptive equalizer, it is possible to correct different types of distortion, caused by the transmission channel, without the need for a training signal. The data processing device according to the invention can thus be used universally for all digital additional signals occurring in a television signal, for example.

Abstract: For the acquisition of multistandard video data a decoder is used with a register 201 having 24 cells for storing 3 times 8 bit of data. Each of the three bytes are connected with logical devices in order to compare the content of the cells with given start codes. Start of the register 202 is byte3, followed by byte2 and byte 1. In addition a second 8 bit register 202 is connected in parallel to the register 201. The content of byte3 is also fed to a Hamming (8/4) decoder 203 and of byte2 to a Hamming (8/4) decoder 204. Each decoder output of 4 bits is fed to the assigned 4 bits of the register 202, respectively.

Abstract: A method for recovering a video signal uses an adaptive equalizer, the characteristics of which are adjusted to the conditions of a transmission channel by using the digital data signals that are concomitantly transmitted in addition to the analogue signal components in a video signal. This adjustment is then used for analogue signal components of the video signals. A teletext signal can advantageously be used for the adjustment.

Abstract: The key component of a digital PAL or NTSC color decoder is a quadrature demodulator for these AM modulated signals. For a SECAM color decoder, however, an FM demodulation is required which is conventionally implemented using a Hilbert filter which is followed by a CORDIC processor and a differentiation stage. It would be advantageous if for multi-standard applications a general-purpose color demodulator for PAL, NTSC and SECAM systems could be implemented on one chip having as much as possible common demodulation processing stages. According to the invention a single common quadrature mixer is used for all three color systems. A resulting bias effect caused by the use of a single mixing frequency is corrected in a clamping stage. The bias effect can also be used for line identification.