Patents by Inventor Jin-chan Ahn

Jin-chan Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784216
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Patent number: 10622231
    Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-chan Ahn, Won-young Kim, Kyung-seon Hwang
  • Publication number: 20190252332
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Patent number: 10297559
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Publication number: 20190115235
    Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.
    Type: Application
    Filed: September 25, 2018
    Publication date: April 18, 2019
    Inventors: Jin-chan AHN, Won-young KIM, Kyung-seon HWANG
  • Patent number: 9780049
    Abstract: A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 3, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-chan Ahn, Sun-won Kang
  • Publication number: 20170133333
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Application
    Filed: October 17, 2016
    Publication date: May 11, 2017
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Publication number: 20140339704
    Abstract: A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 20, 2014
    Inventors: Jin-chan Ahn, Sun-won Kang