Patents by Inventor Jincheng Zhang
Jincheng Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120868Abstract: A massage chair is provided, comprising a body and side plates, the side plates being connected to the body by means of swing rod mechanisms so as to expand the space on two sides of the body by moving from outside to behind relative to the body. The massage chair also comprises limiting mechanisms, the limiting mechanisms being arranged between the body and the swing rod mechanisms, or between the side plates and the swing rod mechanisms. When the swing rod mechanisms are driven by the side plates to switch between different swing states, the limiting mechanisms are correspondingly driven to switch between different limiting states, so as to enable the swing rod mechanisms to correspondingly maintain different swing states.Type: ApplicationFiled: July 6, 2021Publication date: April 17, 2025Applicant: SHANDONG KANGTAI INDUSTRY CO., LTDInventors: Zheng KANG, Zheyi LI, Jincheng ZHANG, Yigang NING, Chongli ZHANG
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Patent number: 12142643Abstract: A material structure for silicon-based gallium nitride microwave and millimeter-wave devices and a manufacturing method thereof are provided. The material structure includes: a silicon substrate; a dielectric layer of high thermal conductivity, disposed on an upper surface of the silicon substrate, and an uneven first patterned interface being formed between the dielectric layer and the silicon substrate; a buffer layer, disposed on an upper surface of the dielectric layer, and an uneven second patterned interface being formed between the buffer layer and the dielectric layer; a channel layer, disposed on an upper surface of the buffer layer; and a composite barrier layer, disposed on an upper surface of the channel layer. In the material structure, the uneven patterned interfaces increase contact areas of the interfaces, a thermal boundary resistance and a thermal resistance of device are reduced, and a heat dissipation performance of device is improved.Type: GrantFiled: March 5, 2021Date of Patent: November 12, 2024Assignee: Xidian UniversityInventors: Jincheng Zhang, Lu Hao, Zhihong Liu, Junwei Liu, Kunlu Song, Yachao Zhang, Weihang Zhang, Yue Hao
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Patent number: 12020925Abstract: A method for preparing an AlN based template having a Si substrate and a method for preparing a GaN based epitaxial structure having a Si substrate are provided. The method for preparing the AlN based template having the Si substrate, which includes: providing the Si substrate; growing an AlN nucleation layer on the Si substrate; and introducing an ion passing through the AlN nucleation layer and into the Si substrate. After the AlN nucleation layer is prepared on the Si substrate, the ions are introduced into the Si substrate and the AlN nucleation layer through the AlN nucleation layer. In this way, types of the introduced ions can be expanded. In addition, a carrier concentration at an interface between the Si substrate and the AlN nucleation layer and a carrier concentration in the AlN nucleation layer can also be reduced.Type: GrantFiled: February 8, 2021Date of Patent: June 25, 2024Assignee: Xidian UniversityInventors: Zhihong Liu, Junwei Liu, Jincheng Zhang, Lu Hao, Kunlu Song, Hong Zhou, Shenglei Zhao, Yachao Zhang, Weihang Zhang, Yue Hao
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Patent number: 11557682Abstract: A low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation and a preparation method thereof. The low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by the present disclosure includes a substrate layer, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are arranged in sequence from bottom to top; a cathode arranged on the AlGaN barrier layer; a groove arranged in the GaN channel layer and the AlGaN barrier layer, and an anode provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer; wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal with a crystal orientation of <100>.Type: GrantFiled: January 19, 2022Date of Patent: January 17, 2023Assignee: XIDIAN UNIVERSITYInventors: Jing Ning, Chi Zhang, Jincheng Zhang, Boyu Wang, Dong Wang, Peijun Ma, Yue Hao
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Patent number: 11538930Abstract: A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which mainly solves a problem that the existing monolithic heterogeneous integrated Cascode-structure field effect transistor has no reverse blocking characteristic. The field effect transistor includes a substrate, a GaN buffer layer, an AlGaN barrier layer and a SiN isolation layer, wherein an isolation groove is etched in the middle of the SiN isolation layer, a Si active layer is printed on the SiN isolation layer on one side of the isolation groove so as to prepare a Si metal oxide semiconductor field effect transistor, and a GaN high-electron-mobility transistor is prepared on the other side of the isolation groove, and a drain electrode of the GaN high-electron-mobility transistor is in Schottky contact with the AlGaN barrier layer to form a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor.Type: GrantFiled: March 15, 2021Date of Patent: December 27, 2022Assignee: Xidian UniversityInventors: Chunfu Zhang, Weihang Zhang, Jiaqi Zhang, Guofang Yang, Yichang Wu, Dazheng Chen, Jincheng Zhang, Yue Hao
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Publication number: 20220310796Abstract: A material structure for silicon-based gallium nitride microwave and millimeter-wave devices and a manufacturing method thereof are provided. The material structure includes: a silicon substrate; a dielectric layer of high thermal conductivity, disposed on an upper surface of the silicon substrate, and an uneven first patterned interface being formed between the dielectric layer and the silicon substrate; a buffer layer, disposed on an upper surface of the dielectric layer, and an uneven second patterned interface being formed between the buffer layer and the dielectric layer; a channel layer, disposed on an upper surface of the buffer layer; and a composite barrier layer, disposed on an upper surface of the channel layer. In the material structure, the uneven patterned interfaces increase contact areas of the interfaces, a thermal boundary resistance and a thermal resistance of device are reduced, and a heat dissipation performance of device is improved.Type: ApplicationFiled: March 5, 2021Publication date: September 29, 2022Inventors: JINCHENG ZHANG, LU HAO, ZHIHONG LIU, JUNWEI LIU, KUNLU SONG, YACHAO ZHANG, WEIHANG ZHANG, YUE HAO
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Publication number: 20220301054Abstract: The invention relates to a block bidding method and system for promoting clean energy consumption based on the power trading platform. The block bidding method includes the following steps: dividing the time slots for clean energy units to participate in power trading; predicting the typical monthly power generation curve of clean energy units; decomposing the signed annual power contract of clean energy units into months; determining the monthly trading declaration curve of clean energy units; determining the monthly trading declaration curve of clean energy units; determining the time-slot declaration price of clean energy units; realizing the trading clearing by the power trading platform in accordance with the principle of “high-low matching”.Type: ApplicationFiled: April 28, 2021Publication date: September 22, 2022Inventors: Lei WANG, Kai XIE, Yali ZHANG, Wujun DONG, Honghai TANG, Ning YANG, Hao TAN, Liang XU, Nan KANG, Peiyu XI, Haining WANG, Shijie JI, Qingbo WANG, Chuncheng GAO, Yin FANG, Shuhong SHI, Mingzhu YUAN, Qian ZHANG, Wentao LV, Jingwei LV, Wanli HU, Ziyang BAI, Junliang LV, Jincheng ZHANG, Xian ZHAO, Xin CHANG, Shulu WAN, Shoubao LI, Ruixiao LI, Ying XUE, Xuan YIN
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Publication number: 20220108885Abstract: A method for preparing an AlN based template having a Si substrate and a method for preparing a GaN based epitaxial structure having a Si substrate are provided. The method for preparing the AlN based template having the Si substrate, which includes: providing the Si substrate; growing an AlN nucleation layer on the Si substrate; and introducing an ion passing through the AlN nucleation layer and into the Si substrate. After the AlN nucleation layer is prepared on the Si substrate, the ions are introduced into the Si substrate and the AlN nucleation layer through the AlN nucleation layer. In this way, types of the introduced ions can be expanded. In addition, a carrier concentration at an interface between the Si substrate and the AlN nucleation layer and a carrier concentration in the AlN nucleation layer can also be reduced.Type: ApplicationFiled: February 8, 2021Publication date: April 7, 2022Inventors: Zhihong LIU, Junwei LIU, Jincheng ZHANG, Lu HAO, Kunlu SONG, Hong ZHOU, Shenglei ZHAO, Yachao ZHANG, Weihang ZHANG, Yue HAO
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Publication number: 20220037515Abstract: A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which mainly solves a problem that the existing monolithic heterogeneous integrated Cascode-structure field effect transistor has no reverse blocking characteristic. The field effect transistor includes a substrate, a GaN buffer layer, an AlGaN barrier layer and a SiN isolation layer, wherein an isolation groove is etched in the middle of the SiN isolation layer, a Si active layer is printed on the SiN isolation layer on one side of the isolation groove so as to prepare a Si metal oxide semiconductor field effect transistor, and a GaN high-electron-mobility transistor is prepared on the other side of the isolation groove, and a drain electrode of the GaN high-electron-mobility transistor is in Schottky contact with the AlGaN barrier layer to form a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor.Type: ApplicationFiled: March 15, 2021Publication date: February 3, 2022Inventors: Chunfu ZHANG, Weihang ZHANG, Jiaqi ZHANG, Guofang YANG, Yichang WU, Dazheng CHEN, Jincheng ZHANG, Yue HAO
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Patent number: 11133185Abstract: The present invention discloses an epitaxial lift-off process of graphene-based gallium nitride (GaN), and principally solves the existing problems about complex lift-off technique, high cost, and poor quality of lift-off GaN films. The invention is achieved by: first, growing graphene on a well-polished copper foil by CVD method; then, transferring a plurality of layers of graphene onto a sapphire substrate; next, growing GaN epitaxial layer on the sapphire substrate with a plurality of graphene layers transferred by the metal organic chemical vapor deposition (MOCVD) method; finally, lifting off and transferring the GaN epitaxial layer onto a target substrate with a thermal release tape. With graphene, the present invention relieves the stress generated by the lattice mismatch between substrate and epitaxial layer; moreover, the present invention readily lifts off and transfers the epitaxial layer to the target substrate by means of weak Van der Waals forces between epitaxial layer and graphene.Type: GrantFiled: June 18, 2020Date of Patent: September 28, 2021Assignee: Xidian UniversityInventors: Jing Ning, Jincheng Zhang, Dong Wang, Yanqing Jia, Chaochao Yan, Boyu Wang, Peijun Ma, Yue Hao
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Patent number: 11031240Abstract: The present invention discloses a method for growing gallium nitride based on graphene and magnetron sputtered aluminum nitride, and a gallium nitride thin film. The method according to an embodiment comprises: spreading graphene over a substrate; magnetron sputtering an aluminum nitrite onto the graphene-coated substrate to obtain a substrate sputtered with aluminum nitrite; placing the substrate sputtered with aluminum nitride into a MOCVD reaction chamber and heat treating the substrate to obtain a heat treated substrate; growing an aluminum nitride transition layer on the heat treated substrate and a first and a second gallium nitride layer having different V-III ratios, respectively.Type: GrantFiled: September 28, 2016Date of Patent: June 8, 2021Assignee: Xidian UniversityInventors: Jincheng Zhang, Jing Ning, Dong Wang, Zhibin Chen, Zhiyu Lin, Yue Hao
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Publication number: 20200402796Abstract: The present invention discloses an epitaxial lift-off process of graphene-based gallium nitride (GaN), and principally solves the existing problems about complex lift-off technique, high cost, and poor quality of lift-off GaN films. The invention is achieved by: first, growing graphene on a well-polished copper foil by CVD method; then, transferring a plurality of layers of graphene onto a sapphire substrate; next, growing GaN epitaxial layer on the sapphire substrate with a plurality of graphene layers transferred by the metal organic chemical vapor deposition (MOCVD) method; finally, lifting off and transferring the GaN epitaxial layer onto a target substrate with a thermal release tape. With graphene, the present invention relieves the stress generated by the lattice mismatch between substrate and epitaxial layer; moreover, the present invention readily lifts off and transfers the epitaxial layer to the target substrate by means of weak Van der Waals forces between epitaxial layer and graphene.Type: ApplicationFiled: June 18, 2020Publication date: December 24, 2020Inventors: Jing Ning, Jincheng Zhang, Dong Wang, Yanqing Jia, Chaochao Yan, Boyu Wang, Peijun Ma, Yue Hao
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Publication number: 20190108999Abstract: The present invention discloses a method for growing gallium nitride based on graphene and magnetron sputtered aluminum nitride, and a gallium nitride thin film. The method according to an embodiment comprises: spreading graphene over a substrate; magnetron sputtering an aluminum nitrite onto the graphene-coated substrate to obtain a substrate sputtered with aluminum nitrite; placing the substrate sputtered with aluminum nitride into a MOCVD reaction chamber and heat treating the substrate to obtain a heat treated substrate; growing an aluminum nitride transition layer on the heat treated substrate and a first and a second gallium nitride layer having different V-III ratios, respectively.Type: ApplicationFiled: September 28, 2016Publication date: April 11, 2019Applicant: XIDIAN UNIVERSITYInventors: Jincheng Zhang, Jing Ning, Dong Wang, Zhibin Chen, Zhiyu Lin, Yue Hao
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Patent number: 9006690Abstract: A method is disclosed for reducing particle contamination in an ion implantation system, wherein an ion beam is created via the ion source operating in conjunction with an extraction electrode assembly. A cathode voltage is applied to the ion source for generating ions therein, and a suppression voltage is applied to the extraction assembly for preventing electrons in the ion beam from being drawn into the ion source. The suppression voltage is selectively modulated, thereby inducing a current flow or an arc discharge through the extraction assembly to remove deposits on surfaces thereof to mitigate subsequent contamination of workpieces.Type: GrantFiled: May 3, 2013Date of Patent: April 14, 2015Assignee: Axcelis Technologies, Inc.Inventors: Neil K. Colvin, Jincheng Zhang
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Publication number: 20140326901Abstract: A method is disclosed for reducing particle contamination in an ion implantation system, wherein an ion beam is created via the ion source operating in conjunction with an extraction electrode assembly. A cathode voltage is applied to the ion source for generating ions therein, and a suppression voltage is applied to the extraction assembly for preventing electrons in the ion beam from being drawn into the ion source. The suppression voltage is selectively modulated, thereby inducing a current flow or an arc discharge through the extraction assembly to remove deposits on surfaces thereof to mitigate subsequent contamination of workpieces.Type: ApplicationFiled: May 3, 2013Publication date: November 6, 2014Inventors: NEIL K. COLVIN, Jincheng Zhang
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Patent number: 8604418Abstract: A method is provided for reducing particle contamination in an ion implantation system, wherein an ion implantation system having source, mass analyzer, resolving aperture, decel suppression plate, and end station is provided. An ion beam is formed via the ion source, and a workpiece is transferred between an external environment and the end station for ion implantation thereto. A decel suppression voltage applied to the decel suppression plate is modulated concurrent with the workpiece transfer, therein causing the ion beam to expand and contract, wherein one or more surfaces of the resolving aperture and/or one or more components downstream of the resolving aperture are impacted by the ion beam, therein mitigating subsequent contamination of workpieces from previously deposited material residing on the one or more surfaces. The contamination can be mitigated by removing the previously deposited material or strongly adhering the previously deposited material to the one or more surfaces.Type: GrantFiled: April 6, 2010Date of Patent: December 10, 2013Assignee: Axcelis Technologies, Inc.Inventors: Neil K. Colvin, Jincheng Zhang
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Publication number: 20110240889Abstract: A method is provided for reducing particle contamination in an ion implantation system, wherein an ion implantation system having source, mass analyzer, resolving aperture, decel suppression plate, and end station is provided. An ion beam is formed via the ion source, and a workpiece is transferred between an external environment and the end station for ion implantation thereto. A decel suppression voltage applied to the decel suppression plate is modulated concurrent with the workpiece transfer, therein causing the ion beam to expand and contract, wherein one or more surfaces of the resolving aperture and/or one or more components downstream of the resolving aperture are impacted by the ion beam, therein mitigating subsequent contamination of workpieces from previously deposited material residing on the one or more surfaces. The contamination can be mitigated by removing the previously deposited material or strongly adhering the previously deposited material to the one or more surfaces.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Applicant: Acelis Technologies. Inc.Inventors: Neil K. Colvin, Jincheng Zhang
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Patent number: D1031666Type: GrantFiled: August 8, 2022Date of Patent: June 18, 2024Assignee: Shen Zhen Broway Electronic Co., Ltd.Inventor: Jincheng Zhang
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Patent number: D1067231Type: GrantFiled: December 7, 2024Date of Patent: March 18, 2025Assignee: Shenzhen Broway Electronic Co., Ltd.Inventors: Jincheng Zhang, Weichang Lai, Rongqin Zhang