Abstract: A high-linearity dynamic amplifier includes a first differential branch and a second differential branch. The first differential branch includes a first MOS transistor and a second MOS transistor which are connected between a high-level terminal and a ground-level terminal in series. A connection point of the first MOS transistor and the second MOS transistor is a second output terminal. The second differential branch includes a third MOS transistor and a fourth MOS transistor which are connected between the high-level terminal and the ground-level terminal in series. A connection point of the third MOS transistor and the fourth MOS transistor is a first output terminal. A grid terminal of the second MOS transistor is connected to a drain terminal of the fourth MOS transistor. A grid terminal of the fourth MOS transistor is connected to a drain terminal of the second MOS transistor.

Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.

Abstract: The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Abstract: The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Abstract: Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor MN1 and MN3 as well as MN2 and MN6, auxiliary buffer comprised of PMOS transistors MP1 and MP3 as well as MP2 and MP4, replica current amplifier comprised of NMOS transistors MN3 and MN4 as well as MN5 and MN6. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.

Abstract: Disclosed are systems, methods, and devices for data anomaly detection. A signal reflective of an input data set having a plurality of dimensions is received. Co-variance across said plurality of dimensions is assessed. Upon said assessing, at least a portion of the input data set is transformed into a dimensionality-reduced data set. For each given data point in the dimensionality-reduced data set, an anomaly score informative of whether said given data point is an anomaly is calculated.

Abstract: The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to ?1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.

Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the variable resistance circuit, and the other end of the variable resistance circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

Abstract: A signal distribution circuit including an equalization circuit, a signal distribution part, an operational amplifying circuit, a feedback circuit, and a time sequence circuit. The equalization circuit is configured to collect an initial broadband signal. The signal distribution part is configured to distribute a first-stage broadband signal resulting from amplitude attenuation process to obtain a plurality of same second-stage broadband signals. The operational amplifying circuit is configured to perform amplification processing on the second-stage broadband signal obtained after distribution to obtain a third-stage broadband signal. The feedback circuit is configured to feedback the third-stage broadband signal to the equalization circuit. The time sequence circuit is configured to adjust an amplification gain of the third-stage broadband signal, and transmit the third-stage broadband signal to an analog to digital converter.

Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

Abstract: A signal distribution circuit including an equalization circuit, a signal distribution part, an operational amplifying circuit, a feedback circuit, and a time sequence circuit. The equalization circuit is configured to collect an initial broadband signal. The signal distribution part is configured to distribute a first-stage broadband signal resulting from amplitude attenuation process to obtain a plurality of same second-stage broadband signals. The operational amplifying circuit is configured to perform amplification processing on the second-stage broadband signal obtained after distribution to obtain a third-stage broadband signal. The feedback circuit is configured to feedback the third-stage broadband signal to the equalization circuit. The time sequence circuit is configured to adjust an amplification gain of the third-stage broadband signal, and transmit the third-stage broadband signal to an analog to digital converter.

Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

Abstract: Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

Abstract: A sampling clock generating circuit and an analog to digital converter includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

Abstract: Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.