Abstract: The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Abstract: A method of failure analysis for locating open circuit defect in a metal layers, comprising: providing a chip sample having a metal layer, with an open circuit defect; delaminating the chip to expose the metal layer; depositing a metal conductive layer on the metal layer; removing a portion of the metal conductive layer to expose the metal layer; depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer; preparing a TEM slice sample which comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer; performing a VC analysis on the TEM slice sample to determine the defect position of the open circuit defect; and analyzing the defect position of the open circuit defect.

Abstract: The present application discloses a method for preparing a TEM sample, comprising: step 1, forming a first protective layer to non-full fill a deep trench; step 2, performing a first time of front and rear side cutting using a FIB, so as to form the TEM sample having a first thickness, and a via in the deep trench is exposed from the front side and the rear side of the TEM sample; step 3, forming a second material layer, which fully fills the exposed via from the front side and the rear side of the TEM sample; and step 4, performing a second time of front and rear side cutting of a target area on the chip sample using the FIB, so as to reduce the thickness of the TEM sample to a target thickness.

Abstract: The present application discloses a method for preparing a TEM sample, comprising: step 1, step 1, providing a chip sample having a metal protective layer formed on a first surface; step 2, fixing the chip sample on a sample table of a FIB system; step 3, performing the first time of FIB cutting on the metal protective layer along a first direction, so as to form a groove, wherein the first direction is the width direction of the TEM sample, and the inner side surface of the groove is arc-shaped so that the thickness of the metal protective layer in a groove area gradually changes; and step 4, performing the second time of FIB cutting along a third direction to thin the chip sample and form the TEM sample, wherein the third direction is a direction from the metal protective layer to the chip sample.

Abstract: The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Abstract: The present application discloses a method for preparing a TEM sample, including the following steps: step 1: providing a thin-film pre-sample with undesirable voids; step 2: performing a first cutting with a first FIB to form the TEM sample located in the target region of the thin-film pre-sample. The first thickness is reached after the first cutting. The voids are exposed from the front surface or the back surface of the TEM sample after the first cutting; step 3: depositing a first material layer by an ALD process to fill the voids in the TEM sample; step 4: performing the second cutting with a second FIB to form the target thickness of the TEM sample in the target region of the thin-film pre-sample. The present application can reduce or eliminate ion beam cutting marks related to the voids in the thin-film pre-sample.

Abstract: The present application discloses a method for preparing a TEM sample, including the following steps: step 1: providing a thin-film pre-sample with undesirable voids; step 2: performing a first cutting with a first FIB to form the TEM sample located in the target region of the thin-film pre-sample. The first thickness is reached after the first cutting. The voids are exposed from the front surface or the back surface of the TEM sample after the first cutting; step 3: depositing a first material layer by an ALD process to fill the voids in the TEM sample; step 4: performing the second cutting with a second FIB to form the target thickness of the TEM sample in the target region of the thin-film pre-sample. The present application can reduce or eliminate ion beam cutting marks related to the voids in the thin-film pre-sample.

Abstract: The present application provides a method for preparing a test sample of a semiconductor device. In an initial orientation, a side surface of the sample substrate exposes a cross section of the semiconductor device to be tested. The semiconductor device has a porous structure on the cross section. Then a filling material is deposited on the porous structure on the cross section to be tested. Next, cutting the sample substrage in a direction perpendicular to the sample substrate, when the sample substrate is in the initial orientation to obtain a sheet test sample, wherein a side surface of the sheet test sample is the cross section to be tested. The method mitigate porous structure effect on a prepared TEM sample, thereby improving quality of a TEM image.

Abstract: The present application provides a method for preparing a test sample of a target semiconductor device, an imaged lateral surface of the sheet test sample exposes a first cross section of a target semiconductor device in the vertical direction; a protective layer is deposited on both sides of the sheet test sample the where the target semiconductor device is located, to longitudinally coat the sheet test sample; and the sheet test sample is longitudinally cut to obtain a columnar test sample. The present application discloses a method to an prepare an ultra-thin sample and perform TEM cross section imaging and analysis on the sample from two directions, thereby improving efficiency in analysis of complex structures and complex defects.