Abstract: A dynamic target tracking method for a robot having multiple joints includes: obtaining a motion state of a tracked dynamic target in real time; performing motion prediction according to the motion state at a current moment to obtain a predicted position of the dynamic target; performing lag compensation on the predicted position to obtain a compensated predicted position; performing on-line trajectory planning according to the compensated predicted position to obtain planning quantities of multi-step joint motion states at multiple future moments, and determining a multi-step optimization trajectory according to the planning quantities and a multi-step optimization objective function; and controlling the joints of the robot to according to the multi-step optimization trajectory.

Abstract: The present disclosure relates to the technical field of mechanical precision manufacturing, in particular to a motor tracking error reduction method and an implementation device based on a micro-drive unit. A motor tracking error reduction method based on micro-drive unit includes: providing a motor mover as the working output end, and feeding back the position information of the motor mover to the micro-drive controller in real time by the sensor; controlling the micro-drive unit to compensate the displacement of the motor mover by the micro-drive controller; correcting the tracking error of the motor mover after the displacement compensation, and feeding back the tracking error information after correction to the motor controller. The error reduction method and implementation device in the present disclosure reduce the motor tracking error and solve the problem of coupling interference. In addition, the single position feedback is used to reduce the production cost.

Abstract: The present disclosure relates to the technical field of mechanical precision manufacturing, in particular to a motor tracking error reduction method and an implementation device based on a micro-drive unit. A motor tracking error reduction method based on micro-drive unit includes: providing a motor mover as the working output end, and feeding back the position information of the motor mover to the micro-drive controller in real time by the sensor; controlling the micro-drive unit to compensate the displacement of the motor mover by the micro-drive controller; correcting the tracking error of the motor mover after the displacement compensation, and feeding back the tracking error information after correction to the motor controller. The error reduction method and implementation device in the present disclosure reduce the motor tracking error and solve the problem of coupling interference. In addition, the single position feedback is used to reduce the production cost.

Abstract: Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.

Abstract: Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

Abstract: Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate.