Abstract: Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Abstract: An embedded magnet frame, an integrated structure and a manufacturing method are disclosed. The manufacturing method includes: manufacturing conductive metal columns, a first sacrificial block and a second sacrificial block on a surface of a bearing plate; laminating a first dielectric layer on the surface of the bearing plate so that the first dielectric layer covers the conductive metal columns, the first sacrificial block and the second sacrificial block; thinning the first dielectric layer to expose surfaces of the conductive metal columns, the first sacrificial block and the second sacrificial block; etching the first sacrificial block and the second sacrificial block to form corresponding first and second mounting cavities, the second mounting cavity being used for mounting a chip; filling the first mounting cavity with magnetic slurry to form an embedded magnet; and removing the bearing plate to form an embedded magnet frame.

Abstract: A manufacturing method for a metal frame chip embedded packaging substrate includes preparing a metal plate, forming a metal frame surrounding a cavity by penetrating the metal plate, and selectively partially etching a first surface of the metal frame to form a first groove on the metal frame, embedding a chip in the cavity so that a patterned side of the chip faces the first surface, and laminating a dielectric layer on a second surface of the metal frame opposite the first surface, the dielectric layer covering a back side of the chip and filling the first groove, forming a blind hole and a window on the dielectric layer, and forming a first wiring layer on the first surface and a second wiring layer on the second surface, the first wiring layer being connected to a terminal of the chip.

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Abstract: Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Abstract: A method for manufacturing a device embedded packaging structure include laminating a first dielectric material on a copper foil to form a first dielectric layer, and forming a first feature pattern in the first dielectric layer to expose the copper foil, etching the exposed copper foil to form a device opening frame and a via post opening frame to obtain a metal frame, applying an adhesive layer on the metal frame, and mounting a device to the adhesive layer in the device opening frame, laminating a second dielectric material to form a second dielectric layer covering the metal frame and filling the device opening frame and the via post opening frame, forming a via post in the via post opening frame, and forming a first wiring layer and a second wiring layer conductively connected by the via post on the upper and lower surfaces of the second dielectric layer.

Abstract: A multichip interconnecting packaging structure includes a glass frame, a first line layer and a second line layer respectively provided on the first surface and the second surface of the glass frame, a first via post penetrating through the glass frame, a cavity penetrating through the glass frame, a chip connecting device embedded in the cavity, a first insulating layer filling the cavity to cover the chip connecting device, and a first chip and a second chip provided on the surface of the first line layer, wherein a terminal of the chip connecting device is connected to the first line layer, the first line layer and the second line layer are in conductive communication through the first via post, the first chip and the second chip are connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip.

Abstract: An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.

Abstract: A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.

Abstract: A carrier plate for preparing a package substrate according to an embodiment includes a dielectric layer, a seed layer in the dielectric layer, and a copper pillar layer on the seed layer. A bottom end of the seed layer is higher than a lower surface of the dielectric layer. A top end of the copper pillar layer is lower than an upper surface of the dielectric layer. The upper and lower surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer.

Abstract: A package substrate and a manufacturing method thereof are disclosed. The method includes: providing an inner substrate; processing an adhesive photosensitive material on a surface of a first side of the inner substrate to obtain an adhesive first insulating dielectric layer; mounting a component on the first insulating dielectric layer; and processing a photosensitive packaging material on the first side of the inner substrate to obtain a second insulating dielectric layer, where the second insulating dielectric layer covers the component.

Abstract: An embedded inductance structure includes an insulating layer, an inductance located in the insulating layer, a multi-layer conducting circuit located in the insulating layer and on the upper surface and lower surface of the insulating layer, and a multi-layer conductive copper column layer located in the insulating layer. The inductance and the multi-layer conducting circuit are conductively connected via the multi-layer conductive copper column layer, and the inductance includes a magnet and an inductance coil in direct contact with the magnet, and the inductance coil is composed of a multi-layer conductive coil and a conductive copper column located between adjacent conductive coils. The multi-layer conductive coils are respectively in a ring shape with a notch and are disconnected at the notch, and the positions of the conductive copper columns located on the upper side and lower of each conductive coil are different in the longitudinal direction.

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure.

Abstract: A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.

Abstract: An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

Abstract: A temporary carrier plate according to an embodiment of the present disclosure includes a first carrier core layer, a first copper foil layer on the first carrier core layer, a second carrier core layer on the first copper foil layer, and a second copper foil layer on the second carrier core layer, wherein the first copper foil layer includes physically press-fitted first outer-layer copper foil and first inner-layer copper foil, and the second copper foil layer includes physically press-fitted second outer-layer copper foil and second inner-layer copper foil.

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Abstract: An embedded packaging structure according to an embodiment of the present disclosure includes an optical communication device embedded in a substrate, and a blocking wall surrounding the working face opening. The optical communication device may include a working face for emitting light or receiving light. The working face may be revealed by a working face opening from a first surface of the substrate. The blocking wall may extend beyond the first surface in a direction away from the first surface.