Patents by Inventor Jindrich Zejda

Jindrich Zejda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100281444
    Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a tag-based engine to track power-domain crossing(s) during graph-based STA. If a power-domain is crossed in a path, pessimism may be added to the cumulative delay at the end point of the path. For those paths that do not cross a power domain, pessimism may be removed from the cumulative delay at their end points. In some embodiments, pessimism may be removed from the cumulative delay at end points for paths that cross power domains.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Jindrich Zejda, William Chiu-Ting Shu, Khalid Rahmat, Feroze Taraporevala
  • Publication number: 20100005429
    Abstract: One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Jindrich Zejda, Narender Hanchate, Rupesh Nayak, Li Ding
  • Publication number: 20090089729
    Abstract: A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Li Ding, Peivand Tehrani, Jindrich Zejda, Alireza Kasnavi
  • Patent number: 7263676
    Abstract: One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 28, 2007
    Assignee: Synopsys, Inc.
    Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Seyed Alireza Kasnavi, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu
  • Patent number: 7007252
    Abstract: One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: February 28, 2006
    Assignee: Synopsys, Inc.
    Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu, Seyed Alireza Kasnavi
  • Publication number: 20040205682
    Abstract: One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Seyed Alireza Kasnavi, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu
  • Publication number: 20040205680
    Abstract: One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.
    Type: Application
    Filed: April 9, 2003
    Publication date: October 14, 2004
    Applicant: Entire Interest
    Inventors: Alexander Gyure, Jindrich Zejda, Peivand Fallah-Tehrani, Wenyuan Wang, Chi-Chong Lo, Mahmoud Shahram, Yansheng Luo, William Chiu-Ting Shu, SEYED ALIREZA KASNAVI