Abstract: A spiking convolutional neural network based on a FLASH storage and computing array, including: a sampling module, a FLASH-based storage and computing array and a corresponding neuron module, and a counter module; the sampling module is used to sample an input image to obtain an input spike; the FLASH-based storage and computing array stores a weight matrix, and is used to perform a vector matrix multiplying operation on the input spike and the weight matrix, and an operation result is output in a form of current; the neuron module is used to integrate the operation result of the FLASH-based storage and computing array so as to generate an output spike; the counter module is used to count a number of spikes generated by the neuron module of an output layer, and determine the number of spikes of the neuron module with a largest number of spikes as a recognition result.

Abstract: A deep neural network based on analog FLASH computing array, includes a number of computing arrays, a number of subtractors, a number of activation circuit units and a number of integral-recognition circuit units. The computing array includes a number of computing units, a number of word lines, a plurality number of bit lines and a number of source lines. Each of the computing units includes a FLASH cell. The gate electrodes of the FLASH cells in the same column are connected to the same word line. The source electrodes of the FLASH cells in the same column are connected to the same source line, and the drain electrodes of the FLASH cells in the same row are connected to the same bit line. Each of the subtractors includes a positive terminal, a negative terminal and an output terminal.

Abstract: A system and a method for compressing an image based on a FLASH in-memory computing array are provided. The system includes: a convolutional neural network for encoding of the FLASH in-memory computing array, a convolutional neural network for decoding based on the FLASH in-memory computing array, and a quantization module; the convolutional neural network for encoding based on the FLASH in-memory computing array is configured to encode an original image to obtain a feature image; the quantization module is configured to quantize the feature image to obtain a quantized image; the convolutional neural network for decoding based on the FLASH in-memory computing array is configured to decode the quantized image to obtain a compressed image.

Abstract: An operating circuit and an operating method of a resistive random-access memory are provided, the operating circuit includes: at least one capacitance connected in series with the resistive random-access memory, so that the resistive random-access memory is grounded through the at least one capacitance. The operating method includes: connecting at least one capacitance in series with a resistive random-access memory, so that the resistive random-access memory is grounded through the capacitance; applying a forming pulse voltage or a set pulse voltage on the resistive random-access memory to achieve a forming operation or a set operation of the resistive random-access memory.

Abstract: The present disclosure relates to the field of semiconductor integrated circuits and manufacturing technologies thereof, and discloses a method and device for realizing a convolution operation based on an NOR flash storage structure. The NOR flash array has a structure of an array composed of a plurality of NOR flash cells. The convolution operation method includes: storing elements of a convolution kernel matrix into the NOR flash cells; converting elements of an input matrix into voltages and applying the voltages to gate terminals of the NOR flash cells; applying a driving voltage to source terminals of the NOR flash cells; and collecting, via drain terminals of the NOR flash cells, current values of each column to obtain a convolution operation result.

Abstract: The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

Abstract: The present disclosure relates to the field of semiconductor integrated circuits and manufacturing technologies thereof, and discloses a method and device for realizing a convolution operation based on an NOR flash storage structure. The NOR flash array has a structure of an array composed of a plurality of NOR flash cells. The convolution operation method includes: storing elements of a convolution kernel matrix into the NOR flash cells; converting elements of an input matrix into voltages and applying the voltages to gate terminals of the NOR flash cells; applying a driving voltage to source terminals of the NOR flash cells; and collecting, via drain terminals of the NOR flash cells, current values of each column to obtain a convolution operation result.

Abstract: The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

Abstract: The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

Abstract: The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.

Abstract: The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

Abstract: A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time tE by using parameters obtained from the fitting. The data retention time of the RRAM device may be predicted by combining voltage acceleration and temperature acceleration.

Abstract: A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element.

Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

Abstract: A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

Abstract: A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (40) and a Schottky diode (30). The Schottky diode (30) and the resistive-switching element (40) are connected in series. The Schottky diode (30) includes a metal layer and a semiconductor layer contacting each other. An interface between the metal layer and the semiconductor layer has a non-planar shape.

Abstract: The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by ‘1’ successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to ‘0’ with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by ‘1’ with a set pulse being applied thereto. In this way, multiary addition operation is implemented.

Abstract: A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

Abstract: A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element.