Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solution for reducing poor contact in InFO package
    Patent number: 10347612
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Package structure and method of manufacturing the same
    Patent number: 10340253
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Method for forming hybrid bonding with through substrate via (TSV)
    Patent number: 10340247
    Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jing-Cheng Lin
  • Through substrate vias with improved connections
    Patent number: 10340205
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Semiconductor Device and Method of Manufacture
    Publication number: 20190189594
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Application
    Filed: December 28, 2018
    Publication date: June 20, 2019
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • METHOD OF FORMING PACKAGE STRUCTURE
    Publication number: 20190172818
    Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng LIN, Po-Hao TSAI
  • Package Structure and Method
    Publication number: 20190164860
    Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 30, 2019
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, Chen-Hua Yu
  • 3D IC architecture with interposer and interconnect structure for bonding dies
    Patent number: 10297550
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Raised via for terminal connections on different planes
    Patent number: 10297494
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kou
  • Semiconductor Device and Method of Manufacture
    Publication number: 20190148288
    Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 16, 2019
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
  • Semiconductor device and manufacturing method of the same
    Patent number: 10290609
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Ying-Ching Shih, Pu Wang, Chen-Hua Yu
  • Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
    Patent number: 10290513
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Thermal dissipation through seal rings in 3DIC structure
    Patent number: 10290559
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Multi-Chip Package and Method of Formation
    Publication number: 20190139922
    Abstract: A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Jui-Pin Hung, Der-Chyang Yeh
  • Alignment Marks in Substrate Having Through-Substrate Via (TSV)
    Publication number: 20190131172
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 2, 2019
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Semiconductor package
    Patent number: 10276516
    Abstract: Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second metal layer. The second metal layer is stacked over the first metal layer and is coupled to the first metal layer through a via. A first semiconductor die is disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL enables fan-out connection of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die and over the RDL. The second semiconductor die is bonded to the RDL by a plurality of conductive bump structures.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • METHODS OF PACKAGING SEMICONDUCTOR DEVICES AND STRUCTURES THEREOF
    Publication number: 20190122929
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung
  • Release Film as Isolation Film in Package
    Publication number: 20190122901
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • PRINTING MODULE, PRINTING METHOD AND SYSTEM OF FORMING A PRINTED STRUCTURE
    Publication number: 20190123015
    Abstract: A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to dispense a first material, a second printing dispenser operable to dispense a second material, a first curing unit, a second curing unit and a third curing unit. The first, the second and the third curing units each is operable to irradiate a light capable of curing the first and second materials and are alternately arranged with the first and second printing dispensers along a line. The first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line. During the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Chih-Chien Pan
  • Rework process and tool design for semiconductor package
    Patent number: 10269762
    Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu