Patents by Inventor Jing-Chuan Hsieh

Jing-Chuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to reduce the depth of a buried contact trench by using a thin split polysilicon thickness
    Patent number: 6001681
    Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: December 14, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang Liu, Jing-Chuan Hsieh