Patents by Inventor Jing-Chyi LIAO

Jing-Chyi LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367788
    Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 21, 2022
    Assignee: MEDIATEK INC.
    Inventors: Jing-Chyi Liao, Ching-Chung Ko, Zheng Zeng
  • Publication number: 20200373428
    Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.
    Type: Application
    Filed: April 21, 2020
    Publication date: November 26, 2020
    Inventors: Jing-Chyi LIAO, Ching-Chung KO, Zheng ZENG