Patents by Inventor Jing-Da LI

Jing-Da LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290884
    Abstract: A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jing-Da Li, Kai-Chuan Kan, Chung-Ren Lao
  • Patent number: 11742389
    Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: August 29, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hung-Chih Tan, Hsing-Chao Liu, Chih-Cherng Liao, Hsiao-Ying Yang, Kai-Chuan Kan, Jing-Da Li
  • Publication number: 20220376052
    Abstract: A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hung-Chih TAN, Hsing-Chao LIU, Chih-Cherng LIAO, Hsiao-Ying YANG, Kai-Chuan KAN, Jing-Da LI