Abstract: A cell region of a semiconductor device includes: substrates, each of which including: substantially uniformly sized clock gate blocks each of which including a clock gate; and substantially uniformly sized decap blocks each of which including a decoupling capacitor. For each substrate, at least one of a condition (A) or a condition (B) is true. The condition (A) includes each row has a first odd-even or a first even-odd intra-row arrangement of the clock gate blocks and the decap blocks, the rows are interleaved with respect to the first odd-even and even-odd intra-row arrangements; and row-wise arrangements of the substrates are different. The condition (B) includes each column has a second odd-even or a second even-odd intra-column arrangement of the clock gate blocks or the decap blocks, the columns are interleaved with respect to the second odd-even and even-odd intra-column arrangements; and column-wise arrangements of the substrates are different.

Abstract: A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.

Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.

Abstract: An IC device includes first and second gate structures; first and second conductors overlying at least a portion of each of the first and second gate structures; a plurality of gate structures between the first and second gate structures; a conductive segment between the first and second conductors and overlying the plurality of gate structures; first and second pluralities of active areas between the first and second gate structures. The first and second pluralities of active areas are between the first and second conductors; a first portion of the plurality of gate structures, a first portion of the first plurality of active areas, and the second plurality of active areas are included in a functional circuit; and a second portion of the plurality of gate structures, a second portion of the first plurality of active areas, and the conductive segment are included in a decoupling capacitor or an antenna diode.

Abstract: The present disclosure provides a lithium iron phosphate battery and a hybrid vehicle. The lithium iron phosphate battery includes a first cathode active material, a second cathode active material, a first anode active material, and a second anode active material. A median particle size of the first cathode active material is different from a median particle size of the second cathode active material. A median particle size of the first anode active material is different from a median particle size of the second anode active material.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.

Abstract: An integrated circuit includes a Schmitt trigger circuit. The Schmitt trigger circuit includes a first, second, third and fourth transistor, a first and second feedback transistor, and a first and second circuit. The first transistor is connected between a first node and a first voltage supply having a first supply voltage. The fourth transistor is connected between the third transistor and a second voltage supply having a second supply voltage. The first circuit is connected to a second node, the first and second voltage supply, and configured to supply the second supply voltage to the second node in response to being enabled. The second feedback transistor is connected to a third node, and a fourth node. The second circuit is connected to the fourth node, the first and second voltage supply, and configured to supply the first supply voltage to the fourth node in response to being enabled.

Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor coupled between the clocking transistor and a first node, and a second enabling transistor coupled between the clocking transistor and a second node. The integrated circuit also includes a branch-one transistor coupled between a first power supply and the first node, and a branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-one transistor is connected to the second node. The gate terminal of the branch-two transistor is connected to the first node. The clocking transistor, the first enabling transistor, and the second enabling transistor are first-type transistors. The branch-one transistor and the branch-two transistor are second-type transistors.

Abstract: An integrated circuit includes a first region including a first set of transistors that include a first set of active regions having a first threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply. The integrated circuit further includes a second region adjacent to the first region. The second region includes a second set of transistors that include a second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.

Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

Abstract: A system and method for cleaning and disinfecting handrail, a robot and passenger conveying equipment. The system for cleaning and disinfecting handrail has at least one robot, the robot including: a travelling device configured to enable the robot to travel along a target trajectory, a cleaning and disinfecting device configured to perform cleaning and disinfection operations on a target object, and a controller connected to the travelling device and the cleaning and disinfecting device and configured to control operation of the travelling device according to command signals such that the robot travels to a target position of the passenger conveying equipment along the target trajectory, and to control the cleaning and disinfecting device to perform cleaning and disinfection operations on the handrail at the target position.

Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.

Abstract: A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.

Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.