Patents by Inventor Jing Ding

Jing Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150063
    Abstract: An integrated circuit includes a first region including a first set of transistors that include a first set of active regions having a first threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply. The integrated circuit further includes a second region adjacent to the first region. The second region includes a second set of transistors that include a second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 8, 2025
    Inventors: Jing DING, Zhang-Ying YAN, Qingchao MENG, Lei PAN
  • Patent number: 12231117
    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: February 18, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: Lei Pan, Yaqi Ma, Jing Ding, Zhang-Ying Yan
  • Patent number: 12224755
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: February 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
  • Patent number: 12191860
    Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: January 7, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITED
    Inventors: Jing Ding, Zhang-Ying Yan, Qingchao Meng, Lei Pan
  • Publication number: 20240199382
    Abstract: A system and method for cleaning and disinfecting handrail, a robot and passenger conveying equipment. The system for cleaning and disinfecting handrail has at least one robot, the robot including: a travelling device configured to enable the robot to travel along a target trajectory, a cleaning and disinfecting device configured to perform cleaning and disinfection operations on a target object, and a controller connected to the travelling device and the cleaning and disinfecting device and configured to control operation of the travelling device according to command signals such that the robot travels to a target position of the passenger conveying equipment along the target trajectory, and to control the cleaning and disinfecting device to perform cleaning and disinfection operations on the handrail at the target position.
    Type: Application
    Filed: August 9, 2023
    Publication date: June 20, 2024
    Inventors: Qing Cheng, Wenhai Yang, Qiping Huang, Jing Ding, Kaisheng Xu
  • Publication number: 20240128956
    Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 18, 2024
    Inventors: Jing DING, Zhang-Ying YAN, Qingchao MENG, Lei PAN
  • Publication number: 20240048135
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Inventors: Huaixin XIAN, Liu HAN, Jing DING, Qingchao MENG
  • Publication number: 20240030920
    Abstract: A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.
    Type: Application
    Filed: October 2, 2023
    Publication date: January 25, 2024
    Inventors: Jing DING, Zhang-Ying YAN, Qingchao MENG, Yi-Ting CHEN
  • Publication number: 20240030921
    Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.
    Type: Application
    Filed: October 6, 2023
    Publication date: January 25, 2024
    Inventors: Ying HUANG, Changlin HUANG, Jing DING, Qingchao MENG
  • Publication number: 20230402446
    Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
  • Patent number: 11843382
    Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: December 12, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITED
    Inventors: Jing Ding, Zhang-Ying Yan, Qingchao Meng, Lei Pan
  • Patent number: 11838026
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
  • Publication number: 20230353143
    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventors: Lei PAN, Yaqi MA, Jing DING, Zhang-Ying YAN
  • Patent number: 11784646
    Abstract: An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 10, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Ying Huang, Changlin Huang, Jing Ding, Qingchao Meng
  • Patent number: 11777501
    Abstract: A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Jing Ding, Zhang-Ying Yan, Qingchao Meng, Yi-Ting Chen
  • Publication number: 20230291394
    Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.
    Type: Application
    Filed: May 4, 2022
    Publication date: September 14, 2023
    Inventors: Jing DING, Zhang-Ying YAN, Qingchao MENG, Lei PAN
  • Patent number: 11695413
    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: July 4, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: Lei Pan, Yaqi Ma, Jing Ding, Zhang-Ying Yan
  • Publication number: 20230089792
    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.
    Type: Application
    Filed: October 22, 2021
    Publication date: March 23, 2023
    Inventors: Lei PAN, Yaqi MA, Jing DING, Zhang-Ying YAN
  • Publication number: 20230029848
    Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 2, 2023
    Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
  • Publication number: 20220405456
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 22, 2022
    Inventors: Huaixin XIAN, Liu HAN, Jing DING, Qingchao MENG