Abstract: A system and method for detecting and correcting bit errors in received packets is disclosed. The presence of bit errors in a received packet are detected using CRC bits carried in the received packet. One or more erroneous bits may be identified in a header of the packet. The erroneous bits are corrected by setting the erroneous bits to match the expected bit settings. The corrected packet is then error-checked using the CRC bits. Errors may be detected in two sequential packets where a second packet is a retransmission of a first packet. Differing bits are identified in the two sequential packets. A packet is modified to include additional combinations of the differing bits and then error-checked with each combination of the differing bits. If a modified packet passes error checking, then process the modified packet.

Abstract: A communication system includes digital transmitter circuitry (26) including a CRC (cyclic redundancy check) generator circuit (28) generating a first CRC code based on a message and appending the CRC code to the message a first data packet, and circuitry (26-1,2,3) transforming the first data packet to provide a second data packet and transmitting it. Digital receiver circuitry (120) includes circuitry (12-1,2,3) receiving the second data packet, a CRC verification circuit (14-1) comparing a received digital CRC code portion of the second data packet to a calculated digital CRC code portion including any introduced error to detect the existence of any error in the second data packet.

Abstract: An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

Abstract: A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel.

Abstract: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

Abstract: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

Abstract: A system and method for classifying packets in a communication network. In one embodiment a packet routing device includes a Bloom filter array and a content-addressable memory (CAM). The Bloom filter array includes a plurality of Bloom filters configured to process a packet in parallel. Each of the Bloom filters is configured to determine whether the packet includes a predetermined attribute. The CAM is coupled to the Bloom filter array. The CAM is configured to assign the packet to an output port of the routing device based on attributes of the packet determined by the Bloom filter array.

Abstract: In at least some embodiments, a method includes receiving a transport block transmission having a plurality of code words and decoding the code words. The method also includes testing each decoded code word to identify each code word as a good code word or a bad code word. During a subsequent retransmission of the transport block, the method includes repeating the decoding and the testing for previously identified bad code words, but not for previously identified good code words.

Abstract: An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable instruction to a processor in response to detecting an instruction request from the processor corresponding to an interrupt response.

Abstract: A device comprising processing logic and transceiver logic coupled to the processing logic. The data is transmitted and received on at least one of a first channel and a second channel. The processing logic determines whether the first channel has been idle for at least a predetermined length of time and determines whether the second channel has been idle for at least another predetermined length of time. Based on these determinations, the transceiver logic transmits data to another device on one or both of the first and second channels.

Abstract: An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one event signal. The control logic provides at least one computer executable instruction to a processor in response to detecting an instruction request from the processor corresponding to an interrupt response.

Abstract: A system 10 for processing data packets according to a CCMP protocol is provided. The system includes a software component 40 operable to form a nonce and an MD according to a CCMP protocol. The system includes a hardware component 20 operable to receive the nonce and AAD and encrypt a portion of the data packet and calculate a MIC according to the CCMP protocol.

Abstract: A virtual input queue 80 count frames of data arriving an input port zo in an Ethernet switch 10 using shared memory 50. The shared memory 50 is allocated among 1-N input ports based on either a static or dynamic memory scheme. The static scheme allocates the shared memory 50 evenly among the input ports 20 or based on the input port transmission rate. In the dynamic memory scheme, the range of a virtual input queue's occupancy is divided into an underload zone, a normal load zone and an overload zone. When the virtual input queue is in the underload zone, the input port is kept on and reserved a memory capacity equal to a low threshold. When a virtual input queue is in the normal load zone, the virtual on queue 80 is reserved an additional amount of memory and the link is kept on or is turned on whenever possible. The memory capacity not used or reserved by any input port operating in at least the underload zone and normal load zone is shared by the input ports operating in the overload zone.

Abstract: A packet switch (26) has N digital input ports (28) each of bandwidth B for receiving data cells including destination addresses for determining output ports, a shared input cache (32), N memory modules (36) of bandwidth N.times.B for buffering, a switch fabric (38), and N digital output ports (40). A digital multiplexer (30) receives each data cell from the input ports (28) and writes it to the shared input cache (32) together with a corresponding port queue number, queue position, and memory module number in response to its destination address so that (1) cells having the same queue number are cyclically assigned to different memory modules (36) and (2) cells having the same queue position are cyclically assigned to different memory modules (36). A digital demultiplexer (34) reads each data cell from the shared input cache (32) and writes it to one of the N memory modules (36) according to its assigned memory module number and queue position.